Method and apparatus for processing an audio video interactive signal

• US 5,539,920 A
• Filed: 04/28/1994
• Issued: 07/23/1996
• Est. Priority Date: 04/28/1994
• Status: Expired due to Term

• Current Assignee: OpenTV, Inc. (Kudelski SA)
• Original Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Inventors: Menand, Jean-Ren e, Delpuch, Alain
• Primary Examiner(s): Kostak, Victor R.
• Assistant Examiner(s): Miller, John W.
• Application Number:
  US08/234,144
• Time in Patent Office: 817 Days
• Field of Search: 348/6, 348/7, 348/10, 348/12, 348/13, 348/461, 348/465, 348/466, 348/467, 455/5.1
• US Class Current: 725/151
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 7/173 with two-way working, e.g. subscriber sending a programme selection signal

Abstract

A method is disclosed for processing modules in an audio video interactive (AVI) receiver receiving a packet service including a plurality of modules, each module having a name and including time multiplexed transmission units, each transmission unit including a header packet containing the name of the module. First a request to perform a process on a module identified by a name is received and an entry containing the received name and requested process is inserted into a list of entries. A header packet in the packet service is then detected. If the name in the detected header packet matches a name in an entry in the list, packet processing circuitry performs the process in the matching entry and a message is sent indicating that the process has been performed.

Claims

1. In an audio video interactive (AVI) receiver receiving a packet service including a plurality of modules, each module having a name and including time multiplexed transmission units, each transmission unit including a header packet containing the name of the module, a method for processing modules comprising steps of:

receiving a request to perform a process on a module identified by a name and inserting in a list of entries an entry containing the received name and requested process;

detecting a header packet in the packet service;

determining if the name in the detected header packet matches a name in an entry in the list;

performing the process in the matching entry if there is a matching entry; and

sending a message indicating that the process has been performed.

2. The method of claim 1 wherein:

the receiving step includes the step of receiving a request to process a complete module; and

the sending step includes the step of removing the matching entry from the list when the complete module has been processed.

3. The method of claim 1 further comprising the step of receiving a request to stop performing a process on a module identified by a name and removing from the list of entries the entry containing the received name and requested process.

4. The method of claim 1 wherein:

each transmission unit further comprises a plurality of data packets associated with each header packet;

the receiving step includes steps of;

receiving a request to process the module by loading the module into a memory; and

allocating a buffer in the memory to contain the module; and

the performing step includes the steps of;

storing each data packet associated with the detected header packet in a respective location in the allocated buffer; and

removing the matching entry in the list when each data packet in each transmission unit in the module has been stored in the allocated buffer.

5. The method of claim 4, wherein:

the plurality of data packets associated with each header packet in a transmission unit contain data in the module located at a respective offset location from the beginning of the module;

the header packet further contains the offset location of the data in the associated plurality of data packets; and

the storing step stores the associated plurality of data packets in the allocated buffer at an offset location equal to the offset location in the header packet.

6. The method of claim 5 wherein:

the packet service continuously and repetitively provides modules carried by successive time multiplexed transmission units containing module data located at sequential offset locations from the beginning of the module;

the detecting step further includes the step of setting a write pointer to the offset location in the detected header packet;

the performing step further comprises the step of saving the offset location in a first detected header packet after a request to load a module has been received as a beginning load location; and

the storing step comprises the steps of;

storing each data packet associated with a detected header packet in the location pointed to by the write pointer;

then updating the write pointer to point to the next sequential location in the allocated buffer after the data packet has been stored;

then comparing the write pointer to the stored beginning load location and performing the removing step when they are equal.

7. The method of claim 6 wherein the detecting step further includes, before the setting step, the steps of:

comparing the write pointer to the offset location in the detected header packet; and

replacing the beginning load location with the offset location in the detected header packet if they are not equal.

8. The method of claim 4 wherein:

each module further includes an embedded error detection code;

the storing step stores the embedded error detection code in the allocated buffer; and

the sending step further includes the steps of;

checking the data in the allocated buffer to detect an error using the embedded error detection code;

sending an error message if an error is detected in the checking step; and

sending a module-loaded message otherwise.

9. The method of claim 8, wherein:

the embedded error detection code is an embedded cyclical redundancy check (CRC) code; and

the checking step calculates a CRC value for the data in the allocated buffer, compares the calculated CRC value to the embedded CRC code and detects an error if they are different.

10. The method of claim 4 wherein

each transmission unit further comprises a plurality of data packets;

the receiving step includes

storing each data packet associated with the detected header packet;

determining if all data packets of a stored transmission unit are error free; and

discarding the entire transmission unit if all data packets of the transmission unit are not error free.

11. The method of claim 1 wherein:

the receiving step includes the step of receiving a request to spy a module in the packet service; and

the performing step includes the step of sending a message whenever there is a matching entry.

12. An audio video interactive (AVI) receiver, comprising:

a source of a packet data stream including a plurality of modules, each module having a name and including time multiplexed transmission units, each transmission unit including a header packet containing the name of the module;

a memory for storing a request queue containing a plurality of entries each including a processing request and a name of a module, and a header packet buffer including a location containing a module name;

request processing circuitry, coupled to the memory, for receiving a request to perform processing on a module identified by a name and storing an entry in the request queue including the name of the identified module and the processing requested;

a header packet memory storage controller, coupled between the data stream source and the memory, for storing header packets in the header packet buffer as they appear in the data stream, and generating a header packet received signal; and

module processing circuitry, responsive to the header packet received signal, for reading the module name from the header packet buffer, comparing the module name to the names in each entry in the request buffer, and if the module name matches an entry name, performing the processing requested in the matching request queue entry, then sending a message.

13. The receiver of claim 12 wherein the module processing circuitry comprises a processor, and the header packet received signal is an interrupt signal for the processor.

14. The receiver of claim 12, wherein the header packet memory storage controller is a direct memory access (DMA) controller.

15. The receiver of claim 12, wherein:

the request processing circuitry receives a request to perform processing on a complete module; and

the module processing circuitry removes the request queue entry after performing the processing requested on the complete module.

16. The receiver of claim 15, wherein:

the memory further stores a module buffer;

the data stream source produces transmission units each further including a plurality of data packets associated with the header packet included in the transmission unit;

the receiver further comprises a module memory storage controller, coupled between the data stream source and the memory, for selectively storing the plurality of data packets from a transmission unit in the module buffer as they appear in the data stream, then generating a data complete signal, in response to an enable signal;

the request processing circuitry receives a processing request to load a complete module, identified by a name, and stores an entry in the request queue containing the identified name and load request; and

the module processing circuitry generates the enable signal if the module name matches an entry name and is responsive to the data complete signal to remove the request queue entry after the complete module is loaded into the module buffer.

17. The receiver of claim 16 wherein:

the data stream source produces each module including an embedded error detection code; and

the module processing circuitry error checks the data in the module buffer after the complete module is loaded into the module buffer using the embedded error detection code, and sends an error message if an error is detected, and a module-loaded message otherwise.

18. The receiver of claim 17, wherein the embedded error detection code is a cyclical redundancy check (CRC) code and the module processing circuitry calculates a CRC value for the data in the module buffer, compares the calculated CRC value to the embedded CRC code and detects an error if they ar different.

19. The receiver of claim 16 wherein:

the data stream source produces successive transmission units containing module data located at sequential offset locations from the beginning of the module, and produces the header packet further containing the offset location of the data in the associated data packets;

the header packet buffer in the memory further includes a location containing the offset location;

the module processing circuitry extracts the offset location from the header packet buffer, and supplies it to the module memory storage controller; and

the module memory storage controller initializes a write pointer with the offset location from the module processing circuitry, loads each data packet into a location in the module buffer pointed to by the write pointer, then updates the write pointer to point to the next sequential location in the module buffer, until all the data packets in a transmission unit have been loaded, then generates the data complete signal.

20. The receiver of claim 19 wherein:

the data stream source continuously and repetitively produces modules;

the memory further contains a beginning load address location; and

the module processing circuitry extracts the offset location from the header packet buffer after the header packet causing a first match has been loaded and saves the offset location in the beginning load address location, and, responsive to the data complete signal from the module memory storage controller, compares the write pointer from the module memory storage controller to the beginning load address location, and sends the message if they are equal.

21. The receiver of claim 20 wherein the module processing circuitry, responsive to the header packet received signal, compares the offset location to the write pointer, and replaces the beginning address location with the offset location if they are not equal.

22. The receiver of claim 16 wherein the module processing circuitry comprises a processor, and the data complete signal is an interrupt signal for the processor.

24. The receiver of claim 12, wherein the request processing circuitry further receives a request to stop processing of a module identified by a name and removes the entry in the request queue including the name of the identified module and the processing requested to stop.

25. The receiver of claim 12, wherein:

the header packet memory storage controller selectively stores header packets in response to an enable signal;

the request processing circuitry generates the enable signal after an entry is stored in the request queue; and

the module processing circuitry further removes the enable signal after the processing has been performed if there are no entries in the request queue.

23. The receiver of 16 wherein the module memory storage controller is a direct memory access (DMA) controller.