Method of fabricating a flip chip semiconductor device having an inductor

• US 5,541,135 A
• Filed: 05/30/1995
• Issued: 07/30/1996
• Est. Priority Date: 05/30/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pfeifer, Michael J., Marlin, George W.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/452,784
• Time in Patent Office: 427 Days
• Field of Search: 437/60, 437/54, 437/182, 437/183, 437/189, 437/192, 437/194, 437/203, 437/209, 251/528, 251/531, 251/532, 251/724, 251/778, 251/924
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Flip chip bumps (24, 26, and 27) and an inductor (17) are simultaneously fabricated on a semiconductor substrate (10). The fabrication process includes two electroplating steps. The first step electroplates copper (18) onto a seed layer (13) to form the inductor (17) and a first portion (16) of the flip chip bumps (24, 26, and 27). The second step electroplates copper (21) onto the previously electroplated copper (18) to form a second portion (21) of the flip chip bumps (24, 26, and 27).

Claims

1. A method of fabricating a semiconductor device having at least one inductor and at least one flip chip bump, the method comprising the steps of:

providing a semiconductor substrate having the semiconductor device;

sputtering titanium tungsten over the semiconductor substrate;

sputtering copper to provide sputtered copper over the titanium tungsten;

covering a first region of the sputtered copper with a first photoresist pattern defining the at least one inductor and the at least one flip chip bump;

electroplating copper to provide electroplated copper over the splattered copper not covered by the first photoresist pattern forming the at least one inductor and a first portion of the at least one flip chip bump;

stripping the first photoresist pattern off of the sputtered copper;

etching away the sputtered copper not covered by the electroplated copper;

covering the at least one inductor and the titanium tungsten with a second photoresist pattern to define a second portion of the at least one flip chip bump over the first portion of the at least one flip chip bump;

electroplating copper over the first portion of the at least one flip chip bump to form the second portion of the at least one flip chip bump;

plating lead over the second portion of the at least one flip chip bump to form a third portion of the at least one flip chip bump;

plating tin over the lead to form a fourth portion of the at least one flip chip bump;

stripping the second photoresist pattern off of the at least one inductor and the titanium tungsten; and

etching away the titanium tungsten not covered by the electroplated copper.

2. The method according to claim 1 further comprising reflowing the at least one flip chip bump.

3. The method according to claim 1 further comprising using ammonium peroxydisulfate for etching the sputtered copper not covered by the electroplated copper.

4. The method according to claim 1 wherein the etching of the sputtered copper further includes selectively etching the sputtered copper over the electroplated copper.

5. The method according to claim 1 further comprising using hydrogen peroxide for etching the titanium tungsten not covered by the sputtered copper.

6. A method of making an electronic device, the method comprising:

providing a substrate;

forming a seed layer over the substrate;

outlining an inductor and a flip chip bump over the seed layer by masking a first region of the seed layer with a first material;

providing a first conductive layer over the seed layer not masked by the first material to form the inductor and a first portion of the flip chip bump;

outlining a second portion of the flip chip bump over the first portion of the flip chip bump by masking the inductor with a second material; and

providing a second conductive layer over the first portion of the flip chip bump to form the second portion of the flip chip bump.

7. The method according to claim 6 further including providing a third conductive layer over the second conductive layer.

8. The method according to claim 7 further providing lead for the third conductive layer.

9. The method according to claim 7 further including providing a fourth conductive layer over the third conductive layer.

10. The method according to claim 9 further providing tin for the fourth conductive layer.

11. The method according to claim 6 further including reflowing the flip chip bump.

12. The method according to claim 6 further including removing the first material from the seed layer prior to outlining the second portion of the flip chip bump over the first portion of the flip chip bump.

13. The method according to claim 12 further including removing at least an upper layer of the seed layer not plated by the first conductive layer after removing the first material from the seed layer and prior to outlining the second portion of the flip chip bump over the first portion of the flip chip bump.

14. The method according to claim 6 further providing titanium tungsten and copper for the seed layer.

15. The method according to claim 6 further including selecting the first and second material from the group consisting of nitride, oxide, polyimide, and photoresist.

16. The method according to claim 6 further providing copper for the first and second conductive layers.

17. The method according to claim 6 wherein the electronic device further contains a semiconductor device electrically coupled to the inductor and the flip chip bump.