Semiconductor device having trench structure

• US 5,541,425 A
• Filed: 12/19/1994
• Issued: 07/30/1996
• Est. Priority Date: 01/20/1994
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nishihara, Hidenori
• Primary Examiner(s): Limanek, Robert P.
• Application Number:
  US08/359,142
• Time in Patent Office: 589 Days
• Field of Search: 257/519, 257/398, 257/397, 257/302, 257/341, 257/330, 257/139, 257/331, 437/38, 148/DIG. 117
• US Class Current: 257/139
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A trench is formed on a main surface of a p+ type monocrystalline silicon substrate. A silicon oxide film is formed extending from the inner surface of trench onto the main surface of p+ type monocrystalline silicon substrate. The thickness of a corner portion positioned on the upper end corner portion of the sidewall of trench in silicon oxide film is larger than the thickness of silicon oxide film positioned on the sidewall of trench. An n type polycrystalline silicon layer extending from the inside of trench onto the main surface of p+ type monocrystalline silicon substrate is formed on silicon oxide film. Thus, a semiconductor device having a trench structure with an improved breakdown voltage for an insulating layer positioned on an upper end corner portion of the sidewall of a trench is obtained.

Claims

1. A semiconductor device having a trench structure, comprising:

a semiconductor substrate having a main surface and a rear surface;

a trench having sidewalls and a rectangular planar shape formed at the main surface of said semiconductor substrate;

an insulating layer formed to extend from the inner surface of said trench onto the main surface of said semiconductor substrate;

an impurity implantation region selectively formed around the upper end portion of the sidewall of the trench and surrounding one end of the trench in the elongate direction; and

a conductive layer formed on said insulating layer filling the trench and extending from the inside of said trench onto the impurity implantation region from the one end of the trench in the elongate direction and onto the main surface of said semiconductor substrate, wherein

the thickness of said insulating layer positioned on an upper end corner portion of a sidewall of said trench covered by said conductive layer and on the impurity implantation region is larger than the thickness of said insulating layer positioned on the sidewall of said trench excluding said upper end corner portion, and the semiconductor device exchanges signals between the main surface and the rear surface of the semiconductor substrate.

2. A semiconductor device having a trench structure as recited in claim 1, wherein

the upper end corner portion of the sidewall of said trench is rounded.

5. A semiconductor device having a trench structure as recited in claim 1, wherein

the thickness of said insulating layer positioned on the upper end corner portion of the sidewall of said trench is at least twice as large as the thickness of said insulating layer positioned on the sidewall of said trench excluding said upper end corner portion.

6. A semiconductor device having a trench structure as recited in claim 1, wherein

in the semiconductor device having said trench structure, an MOS transistor which uses said conductive layer as a gate electrode and said insulating layer as a gate insulating layer is formed, and has a channel formed along a wall surface of said trench.

7. A semiconductor device having a trench structure as recited in claim 1, wherein

on the main surface of said semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on said first semiconductor layer, and a third semiconductor layer of the first conductivity type formed on said second semiconductor layer are formed,

said trench reaches said third semiconductor layer through said first and second semiconductor layers, and

an MOS transistor which uses said conductive layer as a gate electrode, said insulating layer as a gate insulating layer, said first and third semiconductor layers as source/drain regions, and said second semiconductor layer as a channel formation region is formed on the sidewall of said trench.

8. A semiconductor device having a trench structure as recited in claim 7, wherein

a fourth semiconductor layer of the second conductivity type is formed under said first semiconductor layer, said first semiconductor layer functions as an emitter region, and said fourth semiconductor layer functions as a collector region.

9. A semiconductor device having a trench structure as recited in claim 1, wherein

said insulating layer has its thickness increased toward the upper end corner portion of the sidewall of said trench.

10. A semiconductor device having a trench structure as recited in claim 1, wherein

said impurity implanted region has a first end region in the surface of said semiconductor substrate excluding the upper end corner portion of the sidewall of said trench, and a second end region in the surface of the sidewall of said trench excluding the upper end corner portion of the sidewall of said trench, and

said insulating layer has its thickness increased from a portion positioned on said first and second end regions toward the upper end corner portion on the sidewall of said trench.

11. A semiconductor device having a trench structure as recited in claim 2, wherein

said insulating layer is formed by thermally oxidizing the entire main surface of said semiconductor substrate, and on the surface of said impurity implanted region said insulating layer is formed by proliferous oxidation.

12. A semiconductor device having a trench structure as recited in claim 1, wherein

said insulating layer positioned on the sidewall of said trench excluding the upper end corner portion of the sidewall of said trench has a first thickness large enough to function as a gate insulating layer, and

said insulating layer positioned on the upper end corner portion of the sidewall of said trench has a second thickness larger than said first thickness so that breakdown voltage between said conductive layer and said semiconductor substrate is improved.

13. A semiconductor device having a trench structure as recited in claim 1, wherein

the impurity introduced into said impurity implanted region is formed of at least one kind of material selected from the group consisting of As, P, B, BF₂, ions of the material of said semiconductor substrate and ions of a material inert to the material of said semiconductor substrate.

14. A semiconductor device having a trench structure as recited in claim 1, wherein

said insulating layer is formed of a silicon oxide film, and said conductive layer is formed of a polycrystalline silicon layer.

3. A semiconductor device having a trench structure, comprising:

a semiconductor substrate having a main surface;

a trench formed at the main surface of said semiconductor substrate;

an insulating layer formed to extend from the inner surface of said trench onto the main surface of said semiconductor substrate; and

a conductive layer formed on said insulating layer and extending from the inside of said trench onto the main surface of said semiconductor substrate, wherein

the thickness of said insulating layer positioned on an upper end corner portion of a sidewall of said trench covered by said conductive layer is larger than the thickness of said insulating layer positioned on the sidewall of said trench excluding said upper end corner portion, and wherein

the upper end corner portion of the sidewall of said trench is recessed.

4. A semiconductor device having a trench structure as recited in claim 3, wherein

the tip end of a raised portion defining the recess of the upper end corner portion of the sidewall of said trench is rounded.