All MOS single-ended to differential level converter
First Claim
1. An all MOS single-ended to differential level converter comprising:
- first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode;
a current source commonly connected to said drain electrodes of said first and second PMOS semiconductors;
an input circuit for providing to one of said gate electrodes a single-ended input signal and to the other an inverted said single-ended input signal;
first and second load impedences connected to said source electrodes of said first and second PMOS semiconductors, respectively; and
first and second output terminals for providing output analog differential signals at a level which is a function of said load impedances and current source magnitude;
said first output terminal connector to said first load impedance and to said first PMOS semiconductor and said second output terminal connected to said second load impedance and to said second PMOS semiconductor.
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Accused Products
Abstract
An all MOS single-ended to differential level converter including: first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode; a current source commonly connected to the drain electrodes of the first and second PMOS semiconductors; an input circuit for providing to one of the gate electrodes a single-ended input signal and to the other an inverted single-ended input signal; and first and second load impedances connected to the source electrodes of the first and second PMOS semiconductors, respectively, for providing output analog differential signals at a level which is a function of the load impedances and current source magnitude.
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Citations
5 Claims
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1. An all MOS single-ended to differential level converter comprising:
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first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode; a current source commonly connected to said drain electrodes of said first and second PMOS semiconductors; an input circuit for providing to one of said gate electrodes a single-ended input signal and to the other an inverted said single-ended input signal; first and second load impedences connected to said source electrodes of said first and second PMOS semiconductors, respectively; and first and second output terminals for providing output analog differential signals at a level which is a function of said load impedances and current source magnitude;
said first output terminal connector to said first load impedance and to said first PMOS semiconductor and said second output terminal connected to said second load impedance and to said second PMOS semiconductor. - View Dependent Claims (2, 3, 4, 5)
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Specification