W-code enhanced cross correlation satellite positioning system receiver

• US 5,541,606 A
• Filed: 02/02/1995
• Issued: 07/30/1996
• Est. Priority Date: 02/02/1995
• Status: Expired due to Fees

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Lennen, Gary
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): PHAN, DAO LINDA
• Application Number:
  US08/382,889
• Time in Patent Office: 544 Days
• Field of Search: 342/357, 342/352, 455/81
• US Class Current: 342/357.77
• CPC Class Codes: G01S 19/32 Multimode operation in a single same satellite system, e.g. GPS L1/L2
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

The present invention relates to the new W code enhanced GPS receiver which allows to receive and demodulate the L1 and L2 satellite signals encrypted with the unknown Y code. No assumptions are made about the timing or the structure of the unknown Y code. The signal-to noise ration is not compromised in comparison with the reception of the L1 and L2 signals without code encryption.

Claims

1. A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising:

a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite;

wherein said received L1, and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code; and

at least one DIGITAL CHANNEL PROCESSING MEANS for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;

(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal do not contain propagation noise;

(3) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise;

(4) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(5) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code;

(6) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code; and

(7) correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase.

2. The system of claim 1, wherein said RECEIVING MEANS further comprises:

a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals;

a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the noise/signal ratio of the received signals L1 and L2;

a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and

an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1, QL1, IL2, QL2).

3. The system of claim 2 further comprising a MASTER OSCILLATOR MEANS and a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, to said IF PROCESSOR MEANS, to said DOWNCONVERTER MEANS, and to at least one said DIGITAL, CHANNEL PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals.

4. The system of claim 3, wherein said FILTER/LNA MEANS further comprises:

a POWER SPLITTER MEANS connected to said ANTENNA MEANS for power splitting a single L1/L2 signal received by said ANTENNA MEANS into two separate L1 and L2 signals;

two separate BANDPASS FILTER MEANS connected to said POWER SPLITTER MEANS for filtering said L1 and L2 signals independently; and

a POWER COMBINER MEANS connected to said separate BANDPASS FILTER MEANS for power combining said L1 and L2 signals into one combined signal L1/L2 before feeding said combined L1/L2 signal into said LNA;

wherein said LNA outputs amplified and filtered combined L1/L2 signal.

5. The system of claim 3, wherein said FREQUENCY SYNTHESIZER MEANS further comprises:

a PHASE DETECTOR MEANS for comparing phases of two signals, first said signal being an output signal from said MASTER OSCILLATOR MEANS, second said signal being generated by said FREQUENCY SYNTHESIZER MEANS local reference signal, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of said two signals;

a LOOP FILTER MEANS connected to said PHASE DETECTOR MEANS for filtering out high frequency voltage noise, wherein an output LOOP FILTER MEANS voltage signal includes a low frequency voltage noise;

a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS connected to said LOOP FILTER MEANS, wherein a voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output signal is locked to said reference signal; and

wherein said VCO nominal output signal is used as 1st local oscillator (LO1) signal;

a first DIVIDER MEANS connected to said VCO to divide said VCO output signal to obtain 2nd local oscillator (LO2) signal;

a second DIVIDER MEANS connected to said first DIVIDER MEANS to divide said 2nd LO2 signal to obtain sampling clock (SCLK); and

a third DIVIDER MEANS connected to said second DIVIDER MEANS to divide said 2nd LO2 signal to obtain a signal MSEC, wherein said signal MSEC is used for measurement of local reference time.

6. The system of claim 3, wherein said FREQUENCY SYNTHESIZER MEANS further comprises:

a "Divide by 5" block;

a PHASE DETECTOR MEANS connected to said block "Divide by 5" for comparing 5 MHz input signal from said MASTER OSCILLATOR MEANS with 5 MHz signal from said "Divide by 5" block, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of two said 5 MHz signals;

a LOOP FILTER MEANS connected to said PHASE DETECTOR MEANS for filtering out high frequency voltage noise;

a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS connected to said LOOP FILTER MEANS, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output 1400 MHz signal is locked to said 5 MHz reference signal; and

wherein said 1400 MHz VCO output signal is used as a 1st local oscillator (LO1);

a "Divide by 8" block connected to said VCO to divide said 1400MHz VCO output signal by 8 to obtain a 175 MHz signal used as a 2nd LO2;

a "Divide by 7" block connected to said "Divide by 8" block to divide said 175 MHz signal by 7 to obtain a 25 MHz signal used as a sampling clock (SCLK); and

a "Divide by 25000" block connected to said "Divide by 7" block to divide said 25 MHz signal by 25000 to obtain a 1 KHz signal (MSEC), wherein said MSEC signal is used for measurement of local reference time.

7. The system of claim 2, wherein said DOWNCONVERTER MEANS further comprises:

a POWER SPLITTER MEANS connected to said FILTER/LNA MEANS and to said frequency/synthesizer for power splitting said FILTER/LNA MEANS output L1/L2 signal into two signals;

a first MULTIPLIER MEANS connected to said POWER SPLITTER MEANS for multiplying said L1 signal with said 1st LO1 signal, wherein a first mixed signal is produced;

a second MULTIPLIER MEANS connected to said POWER SPLITTER MEANS for multiplying said L2 signal with said 1st LO1 signal, wherein a second mixed signal is produced;

a first BANDPASS FILTER MEANS connected to said first MULTIPLIER MEANS for filtering said first mixed signal;

a second BANDPASS FILTER MEANS connected to said second MULTIPLIER MEANS for filtering said second mixed signal;

a first AMPLIFIER MEANS connected to said first BANDPASS FILTER MEANS for amplifying said first filtered signal; and

a second AMPLIFIER MEANS connected to said second BANDPASS FILTER MEANS for amplifying said second filtered signal.

8. The system of claim 3, wherein said IF PROCESSOR MEANS further comprises:

a first POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals;

a second POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L2 signal into two signals;

a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said 2nd LO2 signal to produce an IL1 signal;

a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said 2nd LO2 signal to produce a QL1 signal;

a third MULTIPLIER MEANS for multiplying said L2 signal with an inphase (I) version of said 2nd LO2 signal to produce an IL2 signal;

a fourth MULTIPLIER MEANS for multiplying said L2 signal with a quadrature (Q) version of said 2nd LO2 signal to produce a QL2 signal;

a first AMPLIFIER MEANS connected to said first MULTIPLIER MEANS for amplifying said IL1 signal;

a second AMPLIFIER MEANS connected to said second MULTIPLIER MEANS for amplifying said QL1 signal;

a third AMPLIFIER MEANS connected to said third MULTIPLIER MEANS for amplifying said IL2 signal;

a fourth AMPLIFIER MEANS connected to said fourth MULTIPLIER MEANS for amplifying said QL2 signal;

a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal;

a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal;

a third one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said third AMPLIFIER MEANS for performing 1-bit quantization operation on said IL2 signal;

a fourth one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said fourth AMPLIFIER MEANS for performing 1-bit quantization operation on said QL2 signal;

a first FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate;

a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

a third FLIP-FLOP MEANS (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock (SCLK) rate; and

.

a fourth FLIP-FLOP MEANS (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate.

9. The system of claim 8, wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises:

an L1 TRACKER MEANS for tracking L1 C/A code when Y code is ON and for tracking L1 P code when Y code is OFF;

an L2 TRACKER MEANS connected to said L1 TRACKER MEANS for tracking an enhanced cross correlated W code when Y code is ON and for tracking L2 P code when Y code is OFF; and

a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said L2 TRACKER MEANS;

wherein said L1 TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and

wherein said L2 TRACKER MEANS is fed by digitized inphase IL2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS; and

wherein each said L1 and L2 TRACKER MEANS are synchronously clocked by said SCLK signal and synchronously referenced by said MSEC signal to local reference time;

said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER MEANS; and

wherein said L2 TRACKER MEANS when Y code is ON is fed from said L1 TRACKER MEANS by generated by said L1 TRACKER MEANS three signals;

L1 P code, filtered estimate of L1 W code, and C/A code epoch (EP code); and

wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS; and

wherein said L1 TRACKER MEANS and said L2 TRACKER MEANS are fed by control signal from said MICROPROCESSOR MEANS.

10. The system of claim 9, wherein said L1 TRACKER MEANS further comprises:

a CODE GENERATOR MEANS for providing a locally generated replica of C/A code and P code;

a MULTIPLEXER MEANS 1 connected to said CODE GENERATOR MEANS for selecting a locally generated code C/A when Y code is ON and for selecting a locally generated P code when Y code is OFF, said MULTIPLEXER MEANS 1 being controlled by said MICROPROCESSOR MEANS system;

a carrier numerically controlled oscillator (CARRIER NCO MEANS1) connected to said MULTIPLEXER MEANS 1;

a CARRIER MIXER MEANS 1 connected to said CARRIER NCO MEANS1 for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and Q L1 signals having carrier frequency with outputted by said CARRIER NCO MEANS1 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS I outputs inphase IL1 and quadrature Q L1 signals having zero carrier frequency;

a CODE MIXER MEANS 1 connected to said CARRIER MIXER MEANS 1, connected to said CODE GENERATOR MEANS and connected to said CARRIER NCO MEANS1 for code correlating said CARRIER MIXER MEANS 1 output signals with said locally generated replica of C/A code;

wherein when said L1 TRACKER MEANS'"'"'s carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a block CORRELATORS MEANS 1 connected to said CODE MIXER MEANS 1 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 1 output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code epoch, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop;

a code numerically controlled oscillator ( CODE NCO MEANS) connected to said block CORRELATORS MEANS 1 and connected to said CODE GENERATOR MEANS for providing a clocking signal at C/A code rate and for providing a clocking signal at P code rate, said C/A code clocking rate and said P code clocking rate driving said CODE GENERATOR MEANS;

said CODE NCO MEANS also providing a mechanism for aligning said locally generated replica of C/A code with said incoming satellite C/A code;

a CODE MIXER MEANS 2 connected to said CARRIER MIXER MEANS 1 and connected to said CODE GENERATOR MEANS, said CARRIER MIXER MEANS I outputting an estimate of L1 Y code as an input to said CODE MIXER MEANS 2, said CODE GENERATOR MEANS outputting said local replica of known L1 P code as input to said CODE MIXER MEANS 2, wherein said CODE MIXER MEANS 2 removes known L1 P code from said estimate of L1 Y code and outputs an estimate of L1 W code;

a DIGITAL DELAY MEANS 1 connected to said CODE MIXER MEANS 2 for delaying under said MICROPROCESSOR MEANS system control said L1 W code estimate;

a DIGITAL FILTER MEANS 1 connected to said DIGITAL DELAY MEANS 1 for reducing the bandwidth of said L1 W code estimate;

wherein said delayed and filtered L1 W code estimate is sent for processing to said L2 TRACKER MEANS;

a DIGITAL DELAY MEANS 2 connected to said CODE GENERATOR MEANS for delaying said P code output from said CODE GENERATOR MEANS, wherein said delayed P code is sent to said L2 TRACKER MEANS; and

a RESOLVER MEANS connected to said CARRIER NCO MEANS 1 for toggling the digital delay between the two delays in the DIGITAL DELAY 1 and in the DIGITAL DELAY 2, wherein the resulting delay is the average of the relative time spent on each said delay;

and wherein said L1 C/A code epoch (EP) is sent to said L2 TRACKER MEANS.

11. The system of claim 10, said L2 TRACKER MEANS further comprising:

a carrier numerically controlled oscillator (CARRIER NCO MEANS2);

a CARRIER MIXER MEANS 2 connected to said CARRIER NCO MEANS2 for mixing outputted by said IF PROCESSOR MEANS digitized inphase I L2 and Q L2 signals having carrier frequency with outputted by said CARRIER NCO MEANS2 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 2 outputs inphase I L2 and quadrature Q L2 signals having zero carrier frequency; and

wherein when L2 carrier tracking loop is locked via said CARRIER NCO MEANS2 said I L2 output contains an estimate of L2 Y code and said Q L2 output contains no signal power;

a CODE MIXER MEANS 3 connected to said CARRIER MIXER MEANS 2 for code correlating said CARRIER MIXER MEANS 2 output I and Q signals with outputted by said L1 TRACKER MEANS P 1 code, wherein said P 1 code represents a locally generated replica of L2 P code, and wherein said CODE MIXER MEANS 3 outputs an I estimate of L2 W code and a Q estimate of L2 W code;

a DIGITAL FILTER MEANS 2 connected to said CODE MIXER MEANS 3 for reducing the bandwidth of said I estimate of L2 W code;

a DIGITAL FILTER MEANS 3 connected to said CODE MIXER MEANS 3 for reducing the bandwidth of said Q estimate of L2 W code;

a CODE MIXER MEANS 4 connected to said DIGITAL FILTER MEANS 2 and connected to said DIGITAL FILTER MEANS 3 for correlating said I estimate of L2 W code and said Q estimate of L2 W code with a signal W1, wherein said signal W1 is said estimate of L1 W code sent by said L1 TRACKER MEANS; and

wherein said CODE MIXER MEANS 4 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a CODE MIXER MEANS 5 connected to said CARRIER MIXER MEANS 2 for code correlating said CARRIER MIXER MEANS 2 output I and Q signals with outputted by said L1 TRACKER MEANS PI code, wherein said P1 code represents a locally generated replica of L2 P code, and wherein said CODE MIXER MEANS 5 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a MULTIPLEXER MEANS 2 connected to said CODE MIXER MEANS 5 and connected to said CODE MIXER MEANS 4 for selecting under the control of MICROPROCESSOR MEANS the mode of operation when Y code is ON and OFF; and

wherein when Y code is OFF and satellite transmits the P code on L2 said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 5; and

wherein when Y code is ON said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 4; and

a block CORRELATORS MEANS 2 connected to said MULTIPLEXER MEANS 2 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 2 output signal is fed to said MICROPROCESSOR MEANS system at a rate of sent by said L1 TRACKER MEANS said L1 C/A code epoch (EP), and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 2 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop.

12. The system of claim 10, wherein said CARRIER NCO MEANS 1 further comprises:

an n-bit ACCUMULATOR MEANS, n being an integer, for adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 1 output frequency word (Q1 . . . Qn) on each sample clock, wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

a first LATCH MEANS 1 connected to said ACCUMULATOR MEANS for latching in said new frequency word B1 . . . Bn under the control signal of said MICROPROCESSOR MEANS, wherein L-top bits of said ACCUMULATOR MEANS output wave are used as said CARRIER NCO MEANS 1 (I) output wave;

L being an integer, L being less than n, L being greater or equal to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS 1 output wave are used as the inphase version (I) of the carrier signal L1 which is phase locked with the satellite signal;

a first ADDER MEANS 1 for adding (01) to the 2-top bits (S1 S2) of the CARRIER NCO MEANS 1 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2);

a third LATCH MEANS 3 connected to said first ADDER MEANS 1 for generating a quadrature version Q of carrier signal L1 by clocking in at the rate of SCLK signal said 2-top bits (R1 R2); and

wherein said LATCH MEANS 3 generates said QL1 signal in the form of L-bit word (R1 R2 S3 . . . SL);

a second LATCH MEANS 2 connected to said ACCUMULATOR MEANS for latching top m bits (C1 . . . Cm), m being an integer (m<

n), of the CARRIER NCO MEANS 1 output signal on the edge of the MSEC timing signal, wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

13. The system of claim 12, wherein said n-bit ACCUMULATOR MEANS with said L-bit output wave further comprises:

a second ADDER MEANS 2 connected to said first LATCH MEANS 1 for adding a frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS1 frequency output (Q1 . . . Qn) on each sample clock; and

a fourth LATCH MEANS 4 connected to said second ADDER MEANS 2 for generating said output CARRIER NCO MEANS1 signal (Q1 . . . Qn), wherein said fourth LATCH MEANS is caused to overflow at the rate of SCLK signal, and wherein L-top output bits of said fourth LATCH MEANS are used as said CARRIER NCO MEANS 1 output signal.

14. The system of claim 11, wherein said CARRIER NCO MEANS2 further comprises:

an n-bit ACCUMULATOR MEANS, n being an integer, for adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS2 output frequency word (Q1 . . . Qn) on each sample clock, wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

a first LATCH MEANS I connected to said ACCUMULATOR MEANS for latching in said new frequency word B1 . . . Bn under the control signal of said MICROPROCESSOR MEANS, wherein L-top bits of said ACCUMULATOR MEANS output wave are used as said CARRIER NCO MEANS2 (I) output wave;

L being an integer, L being less than n, L being greater or equal to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS2 output wave are used as the inphase version (I) of the carrier signal L2 which is phase locked with the satellite signal;

a first ADDER MEANS 1 for adding (01) to the 2-top bits (S1 S2) of the CARRIER NCO MEANS2 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2);

a third LATCH MEANS 3 connected to said first ADDER MEANS 1 for generating a quadrature version Q of carrier signal L2 by clocking in at the rate of SCLK signal said 2-top bits (R1 R2); and

wherein said LATCH MEANS 3 generates said QL2 signal in the form of L-bit word (R1 R2 S3 . . . SL);

a second LATCH MEANS 2 connected to said ACCUMULATOR MEANS for latching top m bits (C1 . . . Cm) of the CARRIER NCO MEANS1 output signal on the edge of the MSEC timing signal, m being an integer, m being less than n;

wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

15. The system of claim 14, wherein said n-bit ACCUMULATOR MEANS with said L-bit output wave further comprises:

a second ADDER MEANS 2 connected to said first LATCH MEANS 1 for adding a frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS2 frequency output (Q1 . . . Qn) on each sample clock; and

a fourth LATCH MEANS 4 connected to said second ADDER MEANS 2 for generating said output CARRIER NCO MEANS2 signal (Q1 . . . Qn), wherein said fourth LATCH MEANS 4 is caused to overflow at the rate of SCLK signal, and wherein L-top output bits of said fourth LATCH MEANS are used as said CARRIER NCO MEANS2 output signal.

16. The system of claim 10, wherein said CARRIER MIXER MEANS 1 further comprises:

a first MULTIPLIER MEANS 1, wherein said first MULTIPLIER MEANS 1 performs a multiplication operation of L-bits of IL1 satellite carrier signal and L-bits of inphase version I of carrier frequency, and wherein said first MULTIPLIER MEANS 1 outputs a (IL1)^* I signal;

a second MULTIPLIER MEANS 2, wherein said second MULTIPLIER MEANS 2 performs a multiplication operation of L-bits of QL1 satellite carrier signal and L-bits of quadrature version Q of carrier frequency, and wherein said second MULTIPLIER MEANS 2 outputs a (QL1)^* Q signal;

a first ADDER MEANS 1 connected to said first MULTIPLIER MEANS 1 and connected to said second MULTIPLIER MEANS 2 for adding said (IL1)^* I signal and said (QL1)^* Q signal;

a third MULTIPLIER MEANS 3, wherein said third MULTIPLIER MEANS 3 performs a multiplication operation of L-bits of IL1 satellite carrier signal and L-bits of quadrature version Q of carrier frequency, and wherein said third MULTIPLIER MEANS 3 outputs a (IL1)^* Q signal;

a fourth MULTIPLIER MEANS 4, wherein said fourth MULTIPLIER MEANS 4 performs a multiplication operation of L-bits of QL1 satellite carrier signal and L-bits of inphase version I of carrier frequency, and wherein said fourth MULTIPLIER MEANS 4 outputs a (QL1)^* I signal; and

a second ADDER MEANS 2 connected to said third MULTIPLIER MEANS 3 and connected to said fourth MULTIPLIER MEANS 4 for subtracting said (QL1)^* I signal from said (IL1)^* Q signal.

17. The system of claim 11, wherein said CARRIER MIXER MEANS 2 further comprises:

a first MULTIPLIER MEANS 1, wherein said first MULTIPLIER MEANS 1 performs a multiplication operation of L-bits of IL2 satellite carrier signal and L-bits of inphase version I of carrier frequency, and wherein said first MULTIPLIER MEANS 1 outputs a (IL2)^* I signal;

a second MULTIPLIER MEANS 2, wherein said second MULTIPLIER MEANS 2 performs a multiplication operation of L-bits of QL2 satellite carrier signal and L-bits of quadrature version Q of carrier frequency, and wherein said second MULTIPLIER MEANS 2 outputs a (QL2)^* Q signal;

a first ADDER MEANS 1 connected to said first MULTIPLIER MEANS 1 and connected to said second MULTIPLIER MEANS 2 for adding said (IL2)^* I signal and said (QL2)^* Q signal;

a third MULTIPLIER MEANS 3, wherein said third MULTIPLIER MEANS 3 performs a multiplication operation of L-bits of IL2 satellite carrier signal and L-bits of quadrature version Q of carrier frequency, and wherein said third MULTIPLIER MEANS 3 outputs a (IL2)^* Q signal;

a fourth MULTIPLIER MEANS 4, wherein said fourth MULTIPLIER MEANS 4 performs a multiplication operation of L-bits of QL2 satellite carrier signal and L-bits of inphase version I of carrier frequency, and wherein said fourth MULTIPLIER MEANS 4 outputs a (QL2)^* I signal; and

a second ADDER MEANS 2 connected to said third MULTIPLIER MEANS 3 and connected to said fourth MULTIPLIER MEANS 4 for subtracting said (QL2)^* I signal from said (IL2)^* Q signal.

18. The system of claim 10, wherein said CODE MIXER MEANS 1 further comprises:

a first MULTIPLIER MEANS 1 for multiplying said incoming I signal with an early version (E) of said local C/A code;

a second MULTIPLIER MEANS 2 for multiplying said incoming I signal with a punctual version (P) of said local C/A code;

a third MULTIPLIER MEANS 3 for multiplying said incoming I signal with a late version (L) of said local C/A code;

a fourth MULTIPLIER MEANS 4 for multiplying said incoming Q signal with an early version (E) of said local C/A code;

a fifth MULTIPLIER MEANS 5 for multiplying said incoming Q signal with a punctual version (P)of said local C/A code; and

a sixth MULTIPLIER MEANS 6 for multiplying said incoming Q signal with a late version (L) of said local C/A code.

19. The system of claim 10, wherein said CODE MIXER MEANS 2 further comprises:

a MULTIPLIER MEANS for multiplying said incoming L1Y code estimate with said locally generated L1P code, wherein said MULTIPLIER MEANS outputs an L1W code estimate.

20. The system of claim 11, wherein said CODE MIXER MEANS 3 further comprises:

a first MULTIPLIER MEANS 1 for multiplying said incoming I estimate of L2Y code with said locally generated P code (P1), wherein said first MULTIPLIER MEANS 1 outputs an I estimate of L2 W code; and

a second MULTIPLIER MEANS 2 for multiplying said incoming Q estimate of L2Y code with said locally generated P code (P1), wherein said second MULTIPLIER MEANS 2 outputs a Q estimate of L2 W code.

21. The system of claim 11, wherein said CODE MIXER MEANS 4 further comprises:

a first MULTIPLIER MEANS 1 for multiplying L-bit of said I estimate of L2 W code at early time point (E) on the autocorrelation function graph with L-bit of said estimate of L1W code, said first MULTIPLIER MEANS creating an early (E) I correlation between estimate of L2 W code and estimate of L1W code;

a second MULTIPLIER MEANS 2 for multiplying L-bit of said I estimate of L2 W code at punctual time point (P) on the autocorrelation function graph with L-bit of said estimate of L1W code, said second MULTIPLIER MEANS creating a punctual (P) I correlation between estimate of L2 W code and estimate of L1W code;

a third MULTIPLIER MEANS 3 for multiplying L-bit of said I estimate of L2 W code at late time point (L) on the autocorrelation function graph with L-bit of said estimate of L1W code, said third MULTIPLIER MEANS 3 creating a late (L) I correlation between estimate of L2 W code and estimate of L1W code;

a fourth MULTIPLIER MEANS 4 for multiplying L-bit of said Q estimate of L2 W code at early time point (E) on the autocorrelation function graph with L-bit of said estimate of L1W code, said fourth MULTIPLIER MEANS 4 creating an early (E) Q correlation between estimate of L2 W code and estimate of L1W code;

a fifth MULTIPLIER MEANS 5 for multiplying L-bit of said Q estimate of L2 W code at punctual time point (P) on the autocorrelation function graph with L-bit of said estimate of L1W code, said fifth MULTIPLIER MEANS 5 creating a punctual (P) Q correlation between estimate of L2 W code and estimate of L1W code; and

a sixth MULTIPLIER MEANS 6 for multiplying L-bit of said Q estimate of L2 W code at late time point (L) on the autocorrelation function graph with L-bit of said estimate of L1W code, said sixth MULTIPLIER MEANS creating a late (L) Q correlation between estimate of L2 W code and estimate of L1W code.

22. The system of claim 12, wherein said CODE MIXER MEANS 5 further comprises:

a first MULTIPLIER MEANS 1 for multiplying said I estimate of L2 W code with an early version (E) of said local P1 code;

a second MULTIPLIER MEANS 2 for multiplying said I estimate of L2 W code with a punctual version (P) of said local P1 code;

a third MULTIPLIER MEANS 3 for multiplying said I estimate of L2 W code with a late version (L) of said local P1 code;

a fourth MULTIPLIER MEANS 4 for multiplying said I estimate of L2 W code with an early version (E) of said local C/A code;

a fifth MULTIPLIER MEANS 5 for multiplying said Q estimate of L2 W code with a punctual version (P) of said local C/A code; and

a sixth MULTIPLIER MEANS 6 for multiplying said Q estimate of L2 W code with a late version (L) of said local C/A code.

23. The system of claim 10, wherein said CODE GENERATOR MEANS further comprises:

a first dividing means for dividing an input signal from said CODE NCO MEANS to provide a C/A CODE GENERATOR MEANS clock signal;

a C/A CODE GENERATOR MEANS connected to said first dividing means for clocking said C/A CODE GENERATOR MEANS clock signal into a C/A code signal and into an EPOCH signal under the control of said MICROPROCESSOR MEANS, wherein said EPOCH signal is used as a timing signal for said CORRELATORS MEANS 1 and said CORRELATORS MEANS 2; and

a P CODE GENERATOR MEANS, wherein said P CODE GENERATOR MEANS is clocked by said CODE NCO MEANS signal under the control of said MICROPROCESSOR MEANS.

24. The system of claim 10, wherein said DIGITAL DELAY MEANS 1 further comprises:

a SHIFT REGISTER MEANS (1 . . . k) for delaying said L-bit L1W code estimate by i-sample clocks, wherein said (i) is an integer greater or equal to 1 and less or equal to k, and wherein said integer (i) is selected under the control of said MICROPROCESSOR MEANS, and wherein said delayed L1W code estimate is aligned with said filtered L2 W code estimate; and

a MULTIPLEXER MEANS for outputting said delayed L1W code estimate.

25. The system of claim 10, wherein said DIGITAL DELAY MEANS 2 further comprises:

a SHIFT REGISTER MEANS (1 . . . k) for delaying said locally generated L1 P code by i-sample clocks, wherein said (i) is an integer greater or equal to 1 and less or equal to k, and wherein said integer (i) is selected under the control of said MICROPROCESSOR MEANS, wherein said delayed locally generated P1 code is aligned with said L2 P code; and

a MULTIPLEXER MEANS for outputting said delayed locally generated P1 code.

26. The system of claim 10, wherein said DIGITAL FILTER MEANS 1 further comprises:

a first L-bit SHIFT REGISTER MEANS (W1,W2, . . . Wx), X being an integer, for making an X- number of delayed copies of said estimate of L1 W code, wherein a first copy L1 W1-code is delayed by one sample clock, a second copy L1 W2-code is delayed by two sample clocks, an (i) copy L1 Wi is delayed by (i) sample clocks, i being an integer, and an x-copy L1 Wx-code is delayed by (x) sample clocks;

an X-number of MULTIPLIER MEANS (C1, . . . Cx), wherein a first MULTIPLIER MEANS C1 transforms said first L1 W1-code into a L1 C1W1-code, wherein a second MULTIPLIER MEANS C2 transforms said second L1 W2-code into a L1 C2W2-code, and wherein an (i) MULTIPLIER MEANS Ci transform said L1 Wi-code into a L1 CiWi code, and wherein an (x) MULTIPLIER MEANS transforms said L1 Wx-code into a L1 CxWx-code;

an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said L1 CiWi-codes into an estimate of the output code function L1 Wout code, wherein said output code function is equal to;

Wout=C1W1+C2W2+ . . . CxWx;

a dividing means for dividing said SCLK signal by K to reduce the rate of said output code function, K being an integer; and

a second k-bit SHIFT REGISTER MEANS, k being an integer (k>

1), connected to said ADDER MEANS for producing an early (E), punctual (P), and a late (L) versions of said estimate L1 of Wout code;

wherein said DIGITAL FILTER MEANS 1 reduces the bandwidth of said L1 W code estimate.

27. The system of claim 11, wherein said DIGITAL FILTER MEANS 2 further comprises:

a first L-bit SHIFT REGISTER MEANS (W1 ,W2, . . . Wx), X being an integer, for making an X- number of delayed copies of said I estimate of L2 W code, wherein a first copy of I estimate of L2 W1-code is delayed by one sample clock, a second copy of I estimate of L2 W2-code is delayed by two sample clocks, an (i) copy of I estimate of L2 Wi is delayed by (i) sample clocks, i being an integer, and an x-copy of I estimate of L2 Wx-code is delayed by (x) sample clocks;

an X-number of MULTIPLIER MEANS (C1, . . . Cx), wherein a first MULTIPLIER MEANS C1 transforms said first I estimate of L2 W 1-code into a L2 C1W1-code, wherein a second MULTIPLIER MEANS C2 transforms said second I estimate of L2 W2-code into a L2 C2W2-code, and wherein an (i) MULTIPLIER MEANS Ci transform said I estimate of L2 Wi-code into a L2 CiWi code, and wherein an (x) MULTIPLIER MEANS transforms said I estimate of L2 Wx -code into an L2 CxWx-code;

an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said L2 CiWi-codes into an I estimate of the output code function L2 Wout code, wherein said output code function is equal to;

Wout=C1W1+C2W2+ . . . CxWx;

a DIVIDING MEANS for dividing said SCLK signal by K to reduce the rate of said output code function, K being an integer; and

a FLIP-FLOP MEANS connected to said DIVIDING MEANS and connected to said ADDER MEANS for reducing the rate of said output code function;

wherein said DIGITAL FILTER MEANS 2 reduces the bandwidth of said I estimate of L2 W code.

28. The system of claim 11, wherein said DIGITAL FILTER MEANS 3 further comprises:

a first L-bit SHIFT REGISTER MEANS (W1,W2, . . . Wx), X being an integer, for making an X- number of delayed copies of said Q estimate of L2 W code, wherein a first copy of Q estimate of L2 W1-code is delayed by one sample clock, a second copy of Q estimate of L2 W2-code is delayed by two sample clocks, an (i) copy of Q estimate of L2 Wi is delayed by (i) sample clocks, i being an integer, and an x-copy of Q estimate of L2 Wx-code is delayed by (x) sample clocks;

an X-number of MULTIPLIER MEANS (C1, . . . Cx), wherein a first MULTIPLIER MEANS C1 transforms said first Q estimate of L2 W1-code into a L2 C1W1-code, wherein a second MULTIPLIER MEANS C2 transforms said second Q estimate of L2 W2-code into a L2 C2W2-code, and wherein an (i) MULTIPLIER MEANS Ci transform said Q estimate of L2 Wi-code into a L2 CiWi code, and wherein an (x) MULTIPLIER MEANS transforms said Q estimate of L2 Wx-code into an L2 CxWx-code;

an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said L2 CiWi-codes into a Q estimate of the output code function L2 Wout code, wherein said output code function is equal to;

Wout=C1W1+C2W2+ . . . CxWx;

a DIVIDING MEANS for dividing said SCLK signal by K to reduce the rate of said output code function;

K being an integer; and

a FLIP-FLOP MEANS connected to said dividing means and connected to said ADDER MEANS for reducing the rate of said output code function;

wherein said DIGITAL FILTER MEANS 3 reduces the bandwidth of said Q estimate of L2 W code.

29. The system of claim 10,

wherein said block CORRELATORS MEANS 1 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) versions of the correlated samples of said L1 C/A (or P) code with said locally generated version of C/A (or P) code across a time period given by a multiple of L1 C/A EPOCH code;

and

wherein said IE,IL,QE, and QL are used by said code tracking loop by forming;

a code phase estimate=K1(IE-IL), when said carrier loop is locked;

or

a code phase estimate=K1[(IE² +QE²)^1/2 -(IL² +QL²)^1/2 ], when said carrier loop is not locked;

where K1 is a L1 code loop gain factor; and

wherein said IP, and QP are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(QP/IP);

said block CORRELATORS MEANS 1 further comprising;

a first UP/DOWN COUNTER MEANS 1 for integrating said IE across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 1 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a first LATCH MEANS connected to said first UP/DOWN COUNTER MEANS 1 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 1 said IE signal;

a second UP/DOWN COUNTER MEANS 2 for integrating said IP across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 2 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a second LATCH MEANS connected to said second UP/DOWN COUNTER MEANS 2 for reading by said, MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 2 said IP signal;

a third UP/DOWN COUNTER MEANS 3 for integrating said IL signal across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 3 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a third LATCH MEANS connected to said third UP/DOWN COUNTER MEANS 3 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 3 said IL signal;

a fourth UP/DOWN COUNTER MEANS 4 for integrating said QE signal across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 4 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a fourth LATCH MEANS connected to said fourth UP/DOWN COUNTER MEANS 4 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 4 said QE signal;

a fifth UP/DOWN COUNTER MEANS 5 for integrating said QP signal across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 5 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a fifth LATCH MEANS connected to said fifth UP/DOWN COUNTER MEANS 5 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 5 said QP signal;

a sixth UP/DOWN COUNTER MEANS 6 for integrating said QL across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 6 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a sixth LATCH MEANS connected to said sixth UP/DOWN COUNTER MEANS 6 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 6 said QL signal.

30. The system of claim 11,

wherein said block CORRELATORS MEANS 2 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) version of the correlated samples between filtered estimate of L1 and L2 W codes across a time period given by a multiple of L1 C/A EPOCH (EP) code;

and

wherein said IE,IL,QE, and QL are used by said code tracking loop by forming;

a code phase estimate=K2(IE-IL), when said carrier loop is locked;

or

a code phase estimate=K2[(IE² +QE²)^1/2 -(IL² +QL²)^1/2 ], when said carrier loop is not locked;

K2 being an L2-code loop gain factor; and

wherein said PQ, and PI codes are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(PQ/PI);

said block CORRELATORS MEANS 2 further comprising;

a first UP/DOWN COUNTER MEANS 1 for integrating said IE across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 1 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a first LATCH MEANS connected to said first UP/DOWN COUNTER MEANS 1 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 1 said IE signal;

a second UP/DOWN COUNTER MEANS 2 for integrating said IP across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 2 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a second LATCH MEANS connected to said second UP/DOWN COUNTER MEANS 2 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 2 said IP signal;

a third UP/DOWN COUNTER MEANS 3 for integrating said IL across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 3 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a third LATCH MEANS connected to said third UP/DOWN COUNTER MEANS 3 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 3 said IL signal;

a fourth UP/DOWN COUNTER MEANS 4 for integrating said QE across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 4 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a fourth LATCH MEANS connected to said fourth UP/DOWN COUNTER MEANS 4 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 4 said QE signal;

a fifth UP/DOWN COUNTER MEANS 5 for integrating said QP across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 5 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a fifth LATCH MEANS connected to said fifth UP/DOWN COUNTER MEANS 5 for reading by said. MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 5 QP signal;

a sixth UP/DOWN COUNTER MEANS 6 for integrating said QL code across a period defined by said C/A EPOCH signal;

wherein said UP/DOWN COUNTER MEANS 6 adds if the input is positive and subtracts if it is negative and is reset on EPOCH; and

a sixth LATCH MEANS connected to said sixth UP/DOWN COUNTER MEANS 6 for reading by said MICROPROCESSOR MEANS system said integrated by said UP/DOWN COUNTER MEANS 6 said QL signal.

31. The system of claim 10, wherein said CODE NCO MEANS provides a clock for said CODE GENERATOR MEANS which generates said locally generated replica of C/A code and P code;

said CODE NCO MEANS further comprising;

a n-bit ACCUMULATOR MEANS, n being an integer, comprising;

a n-bit ADDER MEANS; and

a n-bit LATCH MEANS connected to said n-bit ADDER MEANS; and

a MULTIPLEXER MEANS connected to said n-bit ACCUMULATOR MEANS;

wherein on each sample clock edge the output of said LATCH MEANS is added to the output of said MULTIPLEXER MEANS by said ADDER MEANS;

and wherein said MULTIPLEXER MEANS outputs one of three n-bit values (N,M or SHIFT); and

wherein said CODE NCO MEANS under normal operation outputs;

CODE NCO MEANS frequency=(N×

SCLK)/(2ⁿ -M+N);

and wherein said CODE NCO MEANS under code phase shift operation outputs;

code phase shift=(M-SHIFT)/(2ⁿ -M+N).

32. The system of claim 10, wherein said CODE NCO MEANS provides a clock for said CODE GENERATOR MEANS which generates said locally generated replica of C/A code and P code;

said CODE NCO MEANS further comprising;

a 12-bit ACCUMULATOR MEANS comprising;

a 12-bit ADDER MEANS; and

a 12-bit LATCH MEANS connected to said 12-bit ADDER MEANS; and

a MULTIPLEXER MEANS connected to said 12-bit ACCUMULATOR MEANS;

wherein on each sample clock edge the output of said LATCH MEANS is added to the output of said MULTIPLEXER MEANS by said ADDER MEANS; and

wherein said MULTIPLEXER MEANS outputs one of three 12-bit values (N=1023, M=2619, or SHIFT); and

wherein said CODE NCO MEANS under normal operation outputs;

CODE NCO MEANS frequency=10.23 MHz;

and wherein said CODE NCO MEANS under code phase shift operation outputs;

code phase shift=(2619-SHIFT)/2500 sample clocks.

33. The system of claim 10, wherein said RESOLVER MEANS further comprises:

a COUNTER MEANS;

a COMPARATOR MEANS connected to said COUNTER MEANS; and

a FLIP-FLOP MEANS connected to said. COMPARATOR MEANS;

wherein said COUNTER MEANS is reset every millisecond on the MSEC signal; and

wherein the output state of said FLIP-FLOP MEANS is set to digital 0 every millisecond on the MSEC signal; and

wherein when said COUNTER MEANS reaches a value equal to said COMPARATOR MEANS input value said FLIP-FLOP MEANS is clocked by said COMPARATOR MEANS to the output state equal to digital 1; and

wherein said process is repeated every millisecond; and

wherein said resulting digital delay=(delay 1+(2500-m)/25000),

m being a controllable mark/space ratio; and

wherein said RESOLVER MEANS is used for providing a signal with said controllable mark/space ratio to toggle between said delay 1 and said delay 2.

34. A method for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a correlation processing system;

said system comprising a RECEIVING MEANS and at least one DIGITAL CHANNEL PROCESSING MEANS;

said method comprising the steps of;

providing said RECEIVING MEANS and at least one said DIGITAL, CHANNEL PROCESSING MEANS;

receiving a known C/A code modulated on L1 carrier frequency, an unknown Y code modulated on L1 carrier frequency signal, an unknown Y code modulated on L2 carrier frequency signal by said RECEIVING MEANS;

wherein said received L1, and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code;

generating local replica of said C/A code modulated on L1 carrier frequency signal by each said DIGITAL, CHANNEL PROCESSING MEANS;

generating local replica of said P code modulated on L1 carrier frequency signal by said DIGITAL CHANNEL PROCESSING MEANS;

wherein said locally generated replica of L1 signal do not contain propagation noise;

extracting of an estimate of said Y code from said L1 signal, and from said L2 signal by said DIGITAL CHANNEL PROCESSING MEANS;

wherein said estimate signals contain propagation noise;

correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

removing said P code from said locally extracted estimate of said L1 Y code by said CHANNEL PROCESSOR to obtain a locally extracted estimate of said L1 W code;

removing said P code from said locally extracted estimate of said L2 Y code by said DIGITAL CHANNEL PROCESSOR MEANS to obtain a locally extracted estimate of said L2 W code; and

correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase by said CHANNEL PROCESSOR.

35. The method of claim 34, said RECEIVING MEANS comprising a dual frequency patch ANTENNA MEANS, a FILTER/LNA MEANS, a DOWNCONVERTER MEANS, an IF PROCESSOR MEANS, a MASTER OSCILLATOR MEANS, and a FREQUENCY SYNTHESIZER MEANS;

wherein said step of receiving L1 and L2 satellite signals further comprises the steps of;

receiving said L1 and L2 satellite signals by said dual frequency patch ANTENNA MEANS;

performing filtering and low noise amplification of said L1 and L2 signals by said FILTER/LNA MEANS, wherein said FILTER/LNA MEANS determines the noise/signal ratio of the received signals L1 and L2;

mixing and converting said L1 and L2 signals by said DOWNCONVERTER MEANS;

transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L I and L2 signals (IL1, QL1, IL2, QL2) by said IF PROCESSOR MEANS; and

generating several timing signals by said FREQUENCY SYNTHESIZER MEANS.

36. The method of claim 35, said FILTER/LNA MEANS comprising a POWER SPLITTER MEANS, two separate BANDPASS FILTER MEANS, and a POWER COMBINER MEANS;

said step of performing filtering and low noise amplification of said L1 and L2 signals by said FILTER/LNA MEANS further comprises the steps of;

power splitting said single L1/L2 signal received by said ANTENNA MEANS into two separate L1 and L2 signals by said POWER SPLITTER MEANS;

filtering said L1 and L2 signals independently by said two separate BANDPASS FILTER MEANS;

combining said. L1 and L2 signals into one combined signal L l/L2 before feeding said combined L1/L2 signal into said LNA by said POWER COMBINER MEANS.

37. The method of claim 36, said FREQUENCY SYNTHESIZER MEANS further comprising a PHASE DETECTOR MEANS, a LOOP FILTER MEANS, a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS, a first DIVIDER MEANS, a second DIVIDER MEANS, and a third DIVIDER MEANS;

wherein said step of generating several timing signals by said FREQUENCY SYNTHESIZER MEANS further comprises the steps of;

comparing phases of two signals by said PHASE DETECTOR MEANS, first said signal being an output signal from said MASTER OSCILLATOR MEANS, second said signal being generated by said FREQUENCY SYNTHESIZER MEANS local reference signal, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of said two signals;

filtering out high frequency voltage noise by said LOOP FILTER MEANS, wherein output LOOP FILTER MEANS voltage signal includes a low frequency voltage noise;

generating a 1st local oscillator (LO) signal by said VCO, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output signal is locked to said reference signal;

dividing said 1st LO1 signal by said first DIVIDER MEANS to obtain a 2nd local oscillator (LO2) signal;

dividing said 2nd LO2 signal by said second DIVIDER MEANS to obtain a sampling clock (SCLK); and

dividing said 2nd LO2 signal by said third DIVIDER MEANS to obtain a signal used for measurement of local reference time.

38. The method of claim 36, said FREQUENCY SYNTHESIZER MEANS further comprising a "Divide by 5" block, a PHASE DETECTOR MEANS, a LOOP FILTER MEANS , a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS, a "Divide by 8" block, a "Divide by 7" block, and a "Divide by 25000" block;

wherein said step of generating several timing signals by said FREQUENCY SYNTHESIZER MEANS further comprises the steps of;

comparing 5 MHz input signal from said MASTER OSCILLATOR MEANS with 5 MHz signal from said "Divide by 5" block by said PHASE DETECTOR MEANS, wherein a minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of two said 5 MHz signals;

filtering out high frequency voltage noise by said LOOP FILTER MEANS;

generating a 1st local oscillator (LO1) signal by said VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output 1400 MHz signal is locked to said 5 MHz reference signal; and

wherein said 1400 MHz VCO output signal is used as said 1st local oscillator (LO1);

dividing said 1st LO1 1400 MHz signal by said "Divide by 8" block to obtain a 175 MHz signal, wherein said 175 MHz signal is used as a 2nd LO2 signal;

dividing said 2nd LO2 175 MHz signal by said "Divide by 7" block to obtain a 25 MHz signal, wherein said 25 MHz signal is used as a sampling clock (SCLK); and

dividing said 25 MHz signal by said "Divide by 25000" block to obtain a 1 KHz signal, wherein said 1 KHz signal (MSEC) is used for measurement of local reference time.

39. The method of claim 35, said DOWNCONVERTER MEANS comprising a POWER SPLITTER MEANS, a first MULTIPLIER MEANS, a second MULTIPLIER MEANS, a first BANDPASS FILTER MEANS, a second BANDPASS FILTER MEANS, a first AMPLIFIER MEANS, and a second AMPLIFIER MEANS;

wherein said step of mixing and converting said L1 and L2 signals by said DOWNCONVERTER MEANS further comprises the steps of;

splitting said FILTER/LNA MEANS output L1/L2 signal into two signals L1 and L2 by said POWER SPLITTER MEANS;

producing a first mixed signal by multiplying said L1 signal with said 1st LO1 signal by said first MULTIPLIER MEANS;

producing a second mixed signal by multiplying said L2 signal with said 1st LO1 signal by said second MULTIPLIER MEANS;

filtering said first mixed signal by said first BANDPASS FILTER MEANS;

filtering said second mixed signal by said second BANDPASS FILTER MEANS;

amplifying said first filtered signal by said first AMPLIFIER MEANS; and

amplifying said second filtered signal by said second AMPLIFIER MEANS.

40. The method of claim 35, said IF PROCESSOR MEANS comprising a first POWER SPLITTER MEANS, a second POWER SPLITTER MEANS, a first MULTIPLIER MEANS, a second MULTIPLIER MEANS, a third MULTIPLIER MEANS, a fourth MULTIPLIER MEANS, a first AMPLIFIER MEANS, a second AMPLIFIER MEANS, a third AMPLIFIER MEANS, a fourth AMPLIFIER MEANS, a first one-bit A/D CONVERTER, a second one-bit A/D CONVERTER, a third one-bit A/D CONVERTER, a fourth one-bit A/D CONVERTER, a first FLIP-FLOP MEANS (FF1), a second FF2, a third FF3, and a fourth FF4;

wherein said step of transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1, QL1, IL2, QL2) further comprises the steps of;

splitting said L1 signal into two signals by said first POWER SPLITTER MEANS;

splitting said L2 signal into two signals by said second POWER SPLITTER MEANS;

producing an IL1 signal by multiplying said L1 signal with an inphase (I) version of said 2nd LO2 signal by said first MULTIPLIER MEANS;

producing a QL1 signal by multiplying said L1 signal with a quadrature (Q) version of said 2nd LO2 signal by said second MULTIPLIER MEANS;

producing an IL2 signal by multiplying said L2 signal with an inphase (I) version of said 2nd LO2 signal by said third MULTIPLIER MEANS;

producing a QL2 signal by multiplying said L2 signal with a quadrature (Q) version of said 2nd LO2 signal by said fourth MULTIPLIER MEANS;

amplifying said IL1 signal by said first AMPLIFIER MEANS;

amplifying said QL1 signal by said second AMPLIFIER MEANS;

amplifying said IL2 signal by said third AMPLIFIER MEANS;

amplifying said QL2 signal by said fourth AMPLIFIER MEANS;

performing one-bit quantization operation on said IL1 signal by said first one-bit analog-to-digital (A/D) CONVERTER MEANS;

performing one-bit quantization operation on said QL1 signal by said second one-bit analog-to-digital (A/D) CONVERTER MEANS;

performing one-bit quantization operation on said IL2 signal by said third one-bit analog-to-digital (A/D) CONVERTER MEANS;

performing one-bit quantization operation on said QL2 signal by said fourth one-bit analog-to-digital (A/D) CONVERTER MEANS;

sampling said IL1 signal by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate;

sampling said QL1 signal by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

sampling said IL2 signal by clocking said IL2 signal through said FF3 at sampling clock (SCLK) rate; and

sampling said QL2 signal by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate.

41. The method of claim 34, each said DIGITAL CHANNEL PROCESSING MEANS comprising a L1 TRACKER MEANS, a L2 TRACKER MEANS, and a MICROPROCESSOR MEANS system;

said method further comprising the steps of;

tracking L1 C/A code when Y code is ON and tracking L1 P code when Y code is OFF by said L1 TRACKER MEANS;

tracking an enhanced cross correlated W code when Y code is ON and tracking L2 P code when Y code is OFF by said L2 TRACKER MEANS; and

feeding said MICROPROCESSOR MEANS system by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS.

42. The method of claim 41, said L1 TRACKER MEANS comprising a MULTIPLEXER MEANS 1, a carrier numerically controlled oscillator (CARRIER NCO MEANS1), a CARRIER MIXER MEANS 1, a CODE GENERATOR MEANS, a CODE MIXER MEANS 1, a block CORRELATORS MEANS 1, a code numerically controlled oscillator (CODE NCO MEANS), a CODE MIXER MEANS 2, a DIGITAL DELAY MEANS 1, a DIGITAL FILTER MEANS 1, a RESOLVER MEANS, and a DIGITAL DELAY MEANS 2;

wherein said step of tracking L1 C/A code when Y code is ON and tracking L1 P code when Y code is OFF by said L1 TRACKER MEANS further comprises the steps of;

feeding said L1 TRACKER MEANS by digitized inphase IL1 and quadrature QL1 of L1 signal generated by said IF PROCESSOR MEANS;

synchronously clocking said L1 TRACKER MEANS by said SCLK signal outputted by said FREQUENCY SYNTHESIZER MEANS;

synchronously referencing said L1 TRACKER MEANS by said MSEC signal to local reference time, said MSEC signal being outputted by said FREQUENCY SYNTHESIZER MEANS;

feeding said L1 TRACKER MEANS by control signal from said MICROPROCESSOR MEANS;

providing a locally generated replica of C/A code and locally generated replica of P code by said CODE GENERATOR MEANS;

selecting a locally generated code C/A when Y code is ON and selecting a locally generated P code when Y code is OFF by said MULTIPLEXER MEANS 1;

generating inphase and quadrature components of digital carrier by said CARRIER NCO MEANS1;

generating inphase IL1 and quadrature QL1 signals having zero carrier frequency by mixing digitized inphase IL1 and QL1 signals having carrier frequency with inphase and quadrature components of digital carrier by said CARRIER MIXER MEANS 1;

performing code correlation of said inphase IL1 and quadrature QL1 signals with said locally generated replica of C/A code by said CODE MIXER MEANS 1;

wherein when said L1 TRACKER MEANS carrier tracking loop is closed via said CARRIER NCO MEANS1; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

integrating said early, punctual and late samples of said autocorrelation function by said block CORRELATORS MEANS 1;

feeding said MICROPROCESSOR MEANS system by an output signal of said CORRELATORS MEANS 1 at a rate of L1 C/A code epoch, wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop;

providing a clocking signal at C/A code rate and a clocking signal at P code rate by said code numerically controlled oscillator (CODE NCO MEANS);

driving said CODE GENERATOR MEANS by said C/A code clocking rate and said P code clocking rate;

providing a mechanism for alignment of said locally generated replica of C/A code with said incoming satellite C/A code by said CODE NCO MEANS;

generating an estimate of L1 W code by removing said local replica of L1 P code from said estimate of L1 Y code by said CODE MIXER MEANS 2;

delaying said L1 W code estimate by said DIGITAL DELAY MEANS 1 under said MICROPROCESSOR MEANS system control;

reducing the bandwidth of said L1 W code estimate by said DIGITAL FILTER MEANS 1;

sending said delayed and filtered L1 W code estimate to said L2 TRACKER MEANS;

delaying said P code output from said CODE GENERATOR MEANS by said DIGITAL DELAY MEANS 2;

sending said delayed P code to said L2 TRACKER MEANS;

altering the resulting delay by said RESOLVER MEANS; and

sending said L1 C/A code epoch (EP) to said L2 TRACKER MEANS.

43. The method of claim 41, said L2 TRACKER MEANS comprising a CARRIER NCO MEANS 2, a CARRIER MIXER MEANS 2, a CODE MIXER MEANS 3, a DIGITAL FILTER MEANS 2, a DIGITAL FILTER MEANS 3, a CODE MIXER MEANS 4, a CODE MIXER MEANS 5, a MULTIPLEXER MEANS 2, and a block CORRELATORS MEANS 2;

wherein said step of tracking an enhanced cross correlated W code when Y code is ON and tracking L2 P code when Y code is OFF by said L2 TRACKER MEANS further comprises the steps of;

feeding said L2 TRACKER MEANS by digitized inphase IL2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS;

synchronously clocking said L2 TRACKER MEANS by said SCLK signal outputted by said FREQUENCY SYNTHESIZER MEANS;

synchronously referencing said L2 TRACKER MEANS by said MSEC signal to local reference time, said MSEC signal being outputted by said FREQUENCY SYNTHESIZER MEANS;

feeding said L2 TRACKER MEANS when Y code is ON by said L1 P code, said filtered estimate of L1 W code, and said C/A EP code generated by said L1 TRACKER MEANS;

feeding said L2 TRACKER MEANS by control signal from said MICROPROCESSOR MEANS;

generating IL2 and QL2 signals having carrier frequency by said CARRIER NCO MEANS2;

generating inphase IL2 and quadrature QL2 signals having zero carrier frequency by mixing said digitized inphase IL2 and quadrature QL2 signals having carrier frequency with said inphase and quadrature components IL2 and QL2 of digital carrier generated by said CARRIER MIXER MEANS 2, wherein when L2 carrier tracking loop is locked via said CARRIER NCO MEANS2 said generated IL2 output contains an estimate of L2Y code and said generated QL2 output contains no signal power;

performing code correlation of said IL2 and QL2 having zero frequency signals with outputted by said L1 TRACKER MEANS P1 code by said CODE MIXER MEANS 3;

wherein said P1 code represents a locally generated replica of L2 P code;

generating an I estimate of L2 W code and a Q estimate of L2 W code by said CODE MIXER MEANS 3;

reducing the bandwidth of said I estimate of L2 W code by said DIGITAL FILTER MEANS 2;

reducing the bandwidth of said Q estimate of L2 W code by said DIGITAL FILTER MEANS 3;

performing code correlation of said I estimate of L2 W code and said Q estimate of L2 W code with said estimate of L I W code by said CODE MIXER MEANS 4;

wherein said CODE MIXER MEANS 4 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

performing code correlation of said I estimate of L2 W code and said Q estimate of L2 W code with said P1 code by said CODE MIXER MEANS 5;

wherein said P1 code represents a locally generated replica of L2 P code; and

wherein said CODE MIXER MEANS 5 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

selecting under the control of MICROPROCESSOR MEANS by said MULTIPLEXER MEANS 2 the mode of operation when Y code is ON and OFF; and

wherein when Y code is OFF and satellite transmits the P code on L2 said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 5; and

wherein when Y code is ON said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 4;

integrating early, punctual and late samples of said autocorrelation function by said block CORRELATORS MEANS 2; and

feeding said MICROPROCESSOR MEANS by output signals of said CORRELATORS MEANS 2, wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 2 output signals to develop feedback signals for the carrier tracking loop and for the code tracking loop.

44. The method of claim 42, said CARRIER NCO MEANS1 comprising an n-bit ACCUMULATOR MEANS, n being an integer, a first LATCH MEANS 1, a second LATCH MEANS 2, a first ADDER MEANS 1, a third LATCH MEANS 3, and a second LATCH MEANS 2, wherein said step of generating inphase and quadrature components of digital carrier by said CARRIER NCO MEANS1 further comprises the steps of:

adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS1 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS;

wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

latching in said new frequency word (B1 . . . Bn) under the control signal of said MICROPROCESSOR MEANS by said first LATCH MEANS 1;

wherein L-top bits of said ACCUMULATOR MEANS output wave are used as an inphase version I of said CARRIER NCO MEANS1 output wave;

L being an integer equal or greater to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS1 output wave are used as the inphase version I of the carrier signal L1 which is phase locked with the satellite signal;

adding (01) binary code to the two top bits (S1 S2) of the CARRIER NCO MEANS1 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2) by said first ADDER MEANS 1;

generating a quadrature version Q of carrier signal L1 by clocking in at the rate of the SCLK signal said 2-top bits (R1 R2) by said third LATCH MEANS;

wherein said LATCH MEANS 3 generates said QL1 signal in the from of L-bit word (R1 R2 S3 . . . SL); and

latching top m bits (C1 . . . Cm) of the CARRIER NCO MEANS1 output signal on the edge of the MSEC timing signal by said second LATCH MEANS 2;

m being an integer less than n;

wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

45. The method of claim 44, said n-bit ACCUMULATOR MEANS comprising a second ADDER MEANS 2, and a fourth LATCH MEANS 4, wherein said step of adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO 1 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS further comprises the steps of:

adding said frequency word (B1 . . . Bn) to a previous CARRIER NCO 1 frequency output (Q1 . . . Qn) on each sample clock by said second ADDER MEANS; and

generating said CARRIER NCO MEANS 1 output signal (Q1 . . . Qn) by said fourth LATCH MEANS;

wherein said fourth LATCH MEANS is caused to overflow at the rate of SCLK signal; and

wherein L-top output bits of said fourth LATCH MEANS 4 are used as said CARRIER NCO MEANS 1 output signal.

46. The method of claim 43, said CARRIER NCO MEANS 2 comprising an n-bit ACCUMULATOR MEANS, n being an integer, a first LATCH MEANS 1, a second LATCH MEANS 2, a first ADDER MEANS 1, a third LATCH MEANS 3, and a second LATCH MEANS 2, wherein said step of generating inphase and quadrature components of digital carrier by said CARRIER NCO MEANS 1 further comprises the steps of:

adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 2 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS;

wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

latching in said new frequency word (B1. . . Bn) under the control signal of said MICROPROCESSOR MEANS by said first LATCH MEANS 1;

wherein L-top bits of said ACCUMULATOR MEANS output wave are used as an inphase version I of said CARRIER NCO MEANS 2 output wave;

L being an integer equal or greater to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS 2 output wave are used as the inphase version I of the carrier signal L2 which is phase locked with the satellite signal;

adding (01) binary code to the two top bits (S1 S2) of the CARRIER NCO MEANS 2 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2) by said first ADDER MEANS 1;

generating a quadrature version Q of carrier signal L2 by clocking in at the rate of the SCLK signal said 2-top bits (R1 R2) by said third LATCH MEANS;

wherein said LATCH MEANS 3 generates said QL2 signal in the from of L-bit word (R1 R2 S3 . . . SL); and

latching top m bits (C1 . . . Cm) of the CARRIER NCO MEANS 2 output signal on the edge of the MSEC timing signal by said second LATCH MEANS 2;

m being an integer less than n;

wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

47. The method of claim 46, said n-bit ACCUMULATOR MEANS comprising a second ADDER MEANS 2, and a fourth LATCH MEANS 4, wherein said step of adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 2 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS further comprises the steps of:

adding said frequency word (B1 . . . Bn) to a previous CARRIER NCO MEANS 2 frequency output (Q1 . . . Qn) on each sample clock by said second ADDER MEANS; and

generating said CARRIER NCO MEANS 2 output signal (Q1 . . . Qn) by said fourth LATCH MEANS;

wherein said fourth LATCH MEANS is caused to overflow at the rate of SCLK signal; and

wherein L-top output bits of said fourth LATCH MEANS 4 are used as said CARRIER NCO MEANS 2 output signal.

48. The method of claim 42, said CARRIER MIXER MEANS 1 comprising a first MULTIPLIER MEANS 1, a second MULTIPLIER MEANS 2, a first ADDER MEANS 1, a third MULTIPLIER MEANS 3, a fourth MULTIPLIER MEANS 4 and a second ADDER MEANS 2, wherein said step of generating inphase IL1 and quadrature QL1 signals having zero carrier frequency by mixing digitized inphase IL1 and QL1 signals having carrier frequency with inphase and quadrature components of digital carrier by said CARRIER MIXER MEANS 1 further comprises the steps of:

generating a (IL1)^* I signal by performing a multiplication operation of an inphase version I of L1 satellite carrier signal and an inphase version I of carrier frequency by said first MULTIPLIER MEANS 1;

generating a (QL1 )^* Q signal by performing a multiplication operation of a quadrature version Q of L1 satellite carrier signal and a quadrature version Q of carrier frequency by said second MULTIPLIER MEANS 2,

adding said (IL1)^* I signal and said (QL1)^* Q signal by said first ADDER MEANS 1;

generating a (IL1)^* Q signal by performing a multiplication operation of an inphase version I of L1 satellite carrier signal and a quadrature version Q of carrier frequency by said third MULTIPLIER MEANS 3;

generating a (QL1)^* I signal by performing a multiplication operation of a quadrature version Q of L1 satellite carrier signal and an inphase version I of carrier frequency by said fourth MULTIPLIER MEANS 4; and

subtracting said (QL1)^* I signal from said (IL1)*Q signal by said second ADDER MEANS 2.

49. The method of claim 43, said CARRIER MIXER MEANS 2 comprising a first MULTIPLIER MEANS 1, a second MULTIPLIER MEANS 2, a first ADDER MEANS 1, a third MULTIPLIER MEANS 3, a fourth MULTIPLIER MEANS 4 and a second ADDER MEANS 2, wherein said step of generating inphase IL2 and quadrature QL2 signals having zero carrier frequency by mixing digitized inphase IL2 and QL2 signals having carrier frequency with inphase and quadrature components of digital carrier by said CARRIER MIXER MEANS 2 further comprises the steps of:

generating a (IL2)^* I signal by performing a multiplication operation of an inphase version I of L2 satellite carrier signal and an inphase version I of carrier frequency by said first MULTIPLIER MEANS 1;

generating a (QL2)^* Q signal by performing a multiplication operation of a quadrature version Q of L2 satellite carrier signal and a quadrature version Q of carrier frequency by said second MULTIPLIER MEANS 2,

adding said (IL2)^* I signal and said (QL2)^* Q signal by said first ADDER MEANS 1;

generating a (IL2)^* Q signal by performing a multiplication operation of an inphase version I of L2 satellite carrier signal and a quadrature version Q of carrier frequency by said third MULTIPLIER MEANS 3;

generating a (QL2)^* I signal by performing a multiplication operation of a quadrature version Q of L2 satellite carrier signal and an inphase version I of carrier frequency by said fourth MULTIPLIER MEANS 4; and

subtracting said (QL2)^* I signal from said (IL2)^* Q signal by said second ADDER MEANS 2.

50. The method of claim 42, said CODE MIXER MEANS 1 comprising a first MULTIPLIER MEANS 1, a second MULTIPLIER MEANS 2, a third MULTIPLIER MEANS 3, a fourth MULTIPLIER MEANS, a fifth MULTIPLIER MEANS, and a sixth MULTIPLIER MEANS;

wherein the step of performing code correlation of said inphase IL1 and quadrature QL1 signals with said locally generated replica of C/A code by said CODE MIXER MEANS 1 at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function, further comprises the steps of;

multiplying said incoming I signal with an early version (E) of said local C/A code by said first MULTIPLIER MEANS;

multiplying said incoming I signal with a punctual version (P) of said local C/A code by said second MULTIPLIER MEANS;

multiplying said incoming I signal with a late version (L) of said local C/A code by said third MULTIPLIER MEANS;

multiplying said incoming Q signal with an early version (E) of said local C/A code by said fourth MULTIPLIER MEANS;

multiplying said incoming Q signal with a punctual version (P) of said local C/A code by said fifth MULTIPLIER MEANS; and

multiplying said incoming Q signal with a late version (L) of said local C/A code by said sixth MULTIPLIER MEANS.

51. The method of claim 42, said CODE MIXER MEANS 2 comprising a MULTIPLIER MEANS, said step of generating an estimate of L1 W code by removing said local replica of L1 P code from said estimate of L1 Y code by said CODE MIXER MEANS 2 further comprises the step of:

generating a L1 W code estimate by multiplying said incoming L1 Y code estimate with said locally generated L1 P code by said MULTIPLIER MEANS.

52. The method of claim 43, said CODE MIXER MEANS 3 comprising a first MULTIPLIER MEANS, and a second MULTIPLIER MEANS, wherein said step of performing code correlation of said IL2 and QL2 having zero frequency signals with a locally generated replica L2 P code (P1 code) by said CODE MIXER MEANS 3, further comprises the steps of:

generating an I estimate of L2 W code by multiplying said incoming I estimate of L2 Y code with said locally generated L2 P code (P1 code) by said first MULTIPLIER MEANS; and

generating a Q estimate of L2 W code by multiplying said incoming Q estimate of L2 Y code with said locally generated L2 P code (P1) by said second MULTIPLIER MEANS.

53. The method of claim 43, said CODE MIXER MEANS 4, comprising a first MULTIPLIER MEANS, a second MULTIPLIER MEANS, a third MULTIPLIER MEANS, a fourth MULTIPLIER MEANS, a fifth MULTIPLIER MEANS, and a sixth MULTIPLIER MEANS;

wherein said step of performing correlation of said I estimate of L2 W code and said Q estimate of L2 W code with said estimate of L1 W code by said CODE MIXER MEANS 4 at 3 time points (early, punctual and late) on the autocorrelation graph creating an early, a punctual and a late sample of the autocorrelation function, further comprises the steps of;

multiplying said I estimate of L2 W code at early time point (E) on the autocorrelation function graph with said estimate of L1 W code and creating an early (E) I correlation between estimate of L2 W code and estimate of L1 W code by said first MULTIPLIER MEANS;

multiplying said I estimate of L2 W code at punctual time point (P) on the autocorrelation function graph with said estimate of L1 W code and creating a punctual (P) I correlation between estimate of L2 W code and estimate of L1 W code by said second MULTIPLIER MEANS;

multiplying said I estimate of L2 W code at late time point (L) on the autocorrelation function graph with said estimate of L1 W code and creating a late (L) I correlation between estimate of L2 W code and estimate of L1 W code by said third MULTIPLIER MEANS;

multiplying said Q estimate of L2 W code at early time point (E) on the autocorrelation function graph with said estimate of L1 W code and creating an early (E) Q correlation between estimate of L2 W code and estimate of L1 W code by said fourth MULTIPLIER MEANS;

multiplying said Q estimate of L2 W code at punctual time point (P) on the autocorrelation function graph with said estimate of L1 W code and creating a punctual (P) Q correlation between estimate of L2 W code and estimate of L1 W code by said fifth MULTIPLIER MEANS; and

multiplying said Q estimate of L2 W code at late time point (L) on the autocorrelation function graph with said estimate of L1 W code and creating a late (L) Q correlation between estimate of L2 W code and estimate of L1 W code by said sixth MULTIPLIER MEANS.

54. The method of claim 43, said CODE MIXER MEANS 5 further comprising a first MULTIPLIER MEANS 1, a second MULTIPLIER MEANS 2, a third MULTIPLIER MEANS 3, a fourth MULTIPLIER MEANS 4, a fifth MULTIPLIER MEANS 5, and a sixth MULTIPLIER MEANS 6;

wherein said step of performing of code correlation by said CODE MIXER MEANS 5 at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function, further comprises the steps of;

multiplying said I estimate of L2 W code with an early version (E) of said local P1 code by said first MULTIPLIER MEANS 1;

multiplying said I estimate of L2 W code with a punctual version (P) of said local P1 code by said second MULTIPLIER MEANS 2;

multiplying said I estimate of L2 W code with a late version (L) of said local P1 code by said third MULTIPLIER MEANS 3;

multiplying said I estimate of L2 W code with an early version (E) of said local C/A code by said fourth MULTIPLIER MEANS 4;

multiplying said Q estimate of L2 W code with a punctual version (P) of said local C/A code by said fifth MULTIPLIER MEANS 5; and

multiplying said Q estimate of L2 W code with a late version (L) of said local C/A code by said sixth MULTIPLIER MEANS 6.

55. The method of claim 42, said CODE GENERATOR MEANS comprising a first dividing means, a C/A CODE GENERATOR MEANS, and a P CODE GENERATOR MEANS;

wherein said step of providing a locally generated replica of C/A code by said CODE GENERATOR MEANS further comprises the steps of;

providing a C/A CODE GENERATOR MEANS clock signal by dividing an input signal from said CODE NCO MEANS by said first dividing means;

transforming said C/A CODE GENERATOR MEANS clock signal into a C/A code signal and into an EPOCH signal under the control of said MICROPROCESSOR MEANS by said C/A CODE GENERATOR MEANS, wherein said EPOCH signal is used as a timing signal for said CORRELATORS MEANS 1 and said CORRELATORS MEANS 2; and

clocking said P CODE GENERATOR MEANS by said CODE NCO MEANS signal under the control of said MICROPROCESSOR MEANS.

56. The method of claim 42, said DIGITAL DELAY MEANS 1 comprising a SHIFT REGISTER MEANS (1 . . . k) and a MULTIPLEXER MEANS, wherein said step of delaying said L1 W code estimate by said DIGITAL DELAY MEANS 1 under said MICROPROCESSOR MEANS system control further comprises the steps of:

delaying said locally generated L1 W code estimate by i-sample clocks by said SHIFT REGISTER MEANS (1 . . . k), wherein said (i) is an integer greater or equal to 1 and less or equal to k, and wherein said integer (i) is selected under the control of said MICROPROCESSOR MEANS, and wherein said delayed locally generated L1 W code estimate is aligned with said filtered L2 W code estimate; and

outputting said delayed locally generated L1 W code estimate by said MULTIPLEXER MEANS.

57. The method of claim 42, said DIGITAL DELAY MEANS 2 comprising a SHIFT REGISTER MEANS (1 . . . k), and a MULTIPLEXER MEANS, wherein said step of delaying said P code output from said CODE GENERATOR MEANS by said DIGITAL DELAY MEANS 2 further comprises the steps of:

delaying said locally generated L1 P code by i-sample clocks by said SHIFT REGISTER MEANS (1 . . . k), wherein said (i) is an integer greater or equal to 1 and less or equal to k, and wherein said integer (i) is selected under the control of said. MICROPROCESSOR MEANS, and wherein said delayed locally generated P1 code is aligned with said L2 P code; and

outputting said delayed locally generated P1 code by said MULTIPLEXER MEANS.

58. The method of claim 42, said DIGITAL FILTER MEANS 1 comprising a first L-bit SHIFT REGISTER MEANS, L being an integer, an X-number of MULTIPLIER MEANS, X being an integer, an ADDER MEANS, a dividing means, and a second SHIFT REGISTER MEANS;

wherein said step of reducing the bandwidth of said L1 W code estimate by said DIGITAL FILTER MEANS 1 further comprises the steps of;

making an X- number of delayed copies of said estimate of L1 W code by said first SHIFT REGISTER MEANS (W1,W2, . . . Wx), wherein a first copy L1 W1-code is delayed by one sample clock, a second copy L1 W2-code is delayed by two sample clocks, an (i) copy L1 Wi is delayed by (i) sample clocks, i being an integer, and an x-copy L1 Wx-code is delayed by (x) sample clocks;

transforming said first L1 W1-code into a L1 C1W1-code by said first MULTIPLIER MEANS C1;

transforming said second L1 W2-code into a L1 C2W2-code by said second MULTIPLIER MEANS C2;

performing the transformation of said L1 Wi-code into a L1 CiWi code by said (i) MULTIPLIER MEANS Ci for each (i), wherein said (i) is an integer greater than 1 and less than k;

transforming said L1 Wx-code into a L1 CxWx-code by said (x) MULTIPLIER MEANS Cx;

adding each said L1 CiWi-codes into an estimate of the output code function L1 Wout by said ADDER MEANS, wherein said output code function is equal to;

Wout=C1W1+C2W2+ . . . CxWx;

dividing said SCLK signal by K to reduce the rate of said output code function by said dividing means; and

producing an early (E), punctual (P), and a late (L) versions of said estimate of the output code function L1 Wout-code by said second SHIFT REGISTER MEANS;

wherein said DIGITAL FILTER MEANS 1 reduces the bandwidth of said L1 W code estimate.

59. The method of claim 43, said DIGITAL FILTER MEANS 2 comprising a first L-bit SHIFT REGISTER MEANS, L being an integer, an X-number of MULTIPLIER MEANS, X being an integer, an ADDER MEANS, a dividing means, and a FLIP-FLOP MEANS;

wherein said step of reducing the bandwidth of said I estimate of L2 W code by said DIGITAL FILTER MEANS 2 further comprises the steps of;

making an X- number of delayed copies of said I estimate of L2 W code by said first SHIFT REGISTER MEANS (W1,W2, . . . Wx), wherein a first copy of I estimate of L2 W 1-code is delayed by one sample clock, a second copy of I estimate of L2 W2-code is delayed by two sample clocks, an (i) copy of I estimate of L2 Wi is delayed by (i) sample clocks, i being an integer, and an x-copy of I estimate of L2 Wx-code is delayed by (x) sample clocks;

transforming said first I estimate of L2 W 1-code into a I estimate of L2 C1W1-code by said first MULTIPLIER MEANS C1;

transforming said second I estimate L2 W2-code into a I estimate of L2 C1W2-code by said second MULTIPLIER MEANS C2;

performing the transformation of said I estimate of L2 Wi-code into a I estimate of L2 CiWi code by said (i) MULTIPLIER MEANS Ci for each (i), wherein said i is an integer greater than 1 and less than k;

transforming said I estimate of L2 Wx -code into a I estimate of L2 CxWx-code by said (x) MULTIPLIER MEANS Cx;

adding each said I estimate of L2 CiWi-codes into an I estimate of the output code function L2 Wout-code by said ADDER MEANS, wherein said output code function is equal to;

Wout=C1W1+C2W2+ . . . CxWx;

dividing said SCLK signal by K to reduce the rate of said output code function by said dividing means; and

reducing the rate of said output code function by said FLIP-FLOP MEANS;

wherein said DIGITAL FILTER MEANS 2 reduces the bandwidth of said I estimate of L2 W code.

60. The method of claim 43, said DIGITAL FILTER MEANS 3 comprising a first L-bit SHIFT REGISTER MEANS, L being an integer, an X-number of MULTIPLIER MEANS, X being an integer, an ADDER MEANS, a dividing means, and a FLIP-FLOP MEANS;

wherein said step of reducing the bandwidth of said Q estimate of L2 W code by said DIGITAL FILTER MEANS 3 further comprises the steps of;

making an X- number of delayed copies of said Q estimate of L2 W code by said first SHIFT REGISTER MEANS (W1,W2, . . . Wx), wherein a first copy of Q estimate of L2 W1-code is delayed by one sample clock, a second copy of Q estimate of L2 W2-code is delayed by two sample clocks, an (i) copy of Q estimate of L2 Wi is delayed by (i) sample clocks, i being an integer, and an x-copy of Q estimate of L2 Wx-code is delayed by (x) sample clocks;

transforming said first Q estimate of L2 W 1-code into a Q estimate of L2 C1W1-code by said first MULTIPLIER MEANS C1;

transforming said second Q estimate L2 W2-code into a Q estimate of L2 C2W2-code by said second MULTIPLIER MEANS C2;

performing the transformation of said Q estimate of L2 Wi-code into a Q estimate of L2 CiWi code by said (i) MULTIPLIER MEANS Ci for each (i), wherein said i is an integer greater than 1 and less than k;

transforming said Q estimate of L2 Wx -code into a Q estimate of L2 CxWx-code by said (x) MULTIPLIER MEANS Cx;

adding each said Q estimate of L2 CiWi-codes into an Q estimate of the output code function L2 Wout-code by said ADDER MEANS, wherein said output code function is equal to;

Wout=C1W1+C2W2+ . . . CxWx;

dividing said SCLK signal by K to reduce the rate of said output code function by said dividing means; and

reducing the rate of said output code function by said FLIP-FLOP MEANS;

wherein said DIGITAL FILTER MEANS 3 reduces the bandwidth of said Q estimate of L2 W code.

61. The method of claim 42, said block CORRELATORS MEANS 1 comprising a first UP/DOWN COUNTER MEANS 1, a first LATCH MEANS, a second UP/DOWN COUNTER MEANS 2, a second LATCH MEANS, a third UP/DOWN COUNTER MEANS 3, a third LATCH MEANS, a fourth UP/DOWN COUNTER MEANS 4, a fourth LATCH MEANS, a fifth UP/DOWN COUNTER MEANS 5, a fifth LATCH MEANS, a sixth UP/DOWN COUNTER MEANS 6, and a sixth LATCH MEANS;

wherein said step of integrating said early, punctual and late samples of said autocorrelation function by said block CORRELATORS MEANS 1 further comprises the steps of;

integrating said IE across a period defined by said C/A EPOCH signal by said first UP/DOWN COUNTER MEANS 1;

wherein said UP/DOWN COUNTER MEANS 1 adds if the input is positive and subtracts if it is negative and is reset on EPOCH;

using said first LATCH MEANS for reading said integrated IE signal by said MICROPROCESSOR MEANS system;

integrating said IP across a period defined by said C/A EPOCH signal by said second UP/DOWN COUNTER MEANS 2;

using said second LATCH MEANS for reading said integrated IP signal by said MICROPROCESSOR MEANS system;

integrating said IL across a period defined by said C/A EPOCH signal by said third UP/DOWN COUNTER MEANS;

using said third LATCH MEANS for reading said integrated IL signal by said MICROPROCESSOR MEANS system;

integrating said QE across a period defined by said C/A EPOCH signal by said fourth UP/DOWN COUNTER MEANS 4;

using said fourth LATCH MEANS for reading said integrated QE signal by said MICROPROCESSOR MEANS system;

integrating said QP across a period defined by said C/A EPOCH signal by said fifth UP/DOWN COUNTER MEANS 5;

using said fifth LATCH MEANS for reading said integrated QP signal by said MICROPROCESSOR MEANS system;

integrating said QL across a period defined by said C/A EPOCH signal by said sixth UP/DOWN COUNTER MEANS 6; and

using said sixth LATCH MEANS for reading said integrated QP signal by said MICROPROCESSOR MEANS system;

wherein said block CORRELATORS MEANS 1 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) versions of the correlated samples of said L1 C/A code with said locally generated version of C/A code across a time period given by a multiple of L1 C/A EPOCH code; and

wherein said IE,IL,QE, and QL are used by said code tracking loop by forming;

a code phase estimate=K1(IE-IL), when said carrier loop is locked;

or

a code phase estimate=K1[(IE² +QE²)^1/2 -(IL² +QL²)^1/2 ], when said carrier loop is not locked;

K1 being an L1 code loop gain factor; and

wherein said IP, and QP are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(QP/IP).

62. The method of claim 43, said block CORRELATORS MEANS 2 comprising a first UP/DOWN COUNTER MEANS 1, a first LATCH MEANS, a second UP/DOWN COUNTER MEANS 2, a second LATCH MEANS, a third UP/DOWN COUNTER MEANS 3, a third LATCH MEANS, a fourth up/down COUNTER MEANS 4, a fourth LATCH MEANS, a fifth UP/DOWN COUNTER MEANS 5, a fifth LATCH MEANS, a sixth UP/DOWN COUNTER MEANS 6, and a sixth LATCH MEANS;

wherein said step of integrating said early, punctual and late samples of said autocorrelation function by said block CORRELATORS MEANS 2 further comprises the steps of;

integrating said IE across a period defined by said C/A EPOCH signal by said first UP/DOWN COUNTER MEANS 1;

wherein said UP/DOWN COUNTER MEANS adds if the input is positive and subtracts if it is negative and is reset on EPOCH;

using said first LATCH MEANS for reading said integrated IE signal by said MICROPROCESSOR MEANS system;

integrating said IP across a period defined by said C/A EPOCH signal by said second UP/DOWN COUNTER MEANS 2;

using said second LATCH MEANS for reading said integrated IP signal by said MICROPROCESSOR MEANS system;

integrating said IL across a period defined by said C/A EPOCH signal by said third UP/DOWN COUNTER MEANS 3;

using said third LATCH MEANS for reading said integrated IL signal by said MICROPROCESSOR MEANS system;

integrating said QE across a period defined by said C/A EPOCH signal by said fourth UP/DOWN COUNTER MEANS 4;

using said fourth LATCH MEANS for reading said integrated QE signal by said MICROPROCESSOR MEANS system;

integrating said QP across a period defined by said C/A EPOCH signal by said fifth UP/DOWN COUNTER MEANS 5;

using said fifth LATCH MEANS for reading said integrated QP signal by said MICROPROCESSOR MEANS system;

integrating said QL across a period defined by said C/A EPOCH signal by said sixth UP/DOWN COUNTER MEANS; and

using said sixth LATCH MEANS for reading said integrated QL signal by said MICROPROCESSOR MEANS system;

wherein said block CORRELATORS MEANS 2 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) version of the correlated samples between filtered estimates of L1 and L2 W codes across a time period given by a multiple of L2 C/A EPOCH code; and

wherein said IE,IL,QE, and QL are used by said code tracking loop by forming;

a code phase estimate=K2(IE-IL), when said carrier loop is locked;

or

a code phase estimate=K2[(IE² +QE²)^1/2 -(IL² +QL²)^1/2], when said carrier loop is not locked;

K2 being an L2 code loop gain factor; and

wherein said IP, and QP signals are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(QP/IP).

63. The method of claim 42, said CODE NCO MEANS comprising a n-bit ACCUMULATOR MEANS, a n-bit LATCH MEANS, n being an integer, and a MULTIPLEXER MEANS;

wherein said step of providing a clocking signal at C/A code rate and a clocking signal at P code rate for said CODE GENERATOR MEANS by said CODE NCO MEANS further comprises the steps of;

adding on each sample clock edge the output of said LATCH MEANS to the output of said MULTIPLEXER MEANS by said ACCUMULATER;

generating one of three n-bit values (N,M or SHIFT) by said MULTIPLEXER MEANS;

outputting under normal operation CODE NCO MEANS frequency=(N×

SCLK)/(2ⁿ -M+N) by said CODE NCO MEANS; and

outputting under code phase shift operation code phase shift=(M-SHIFT)/(2ⁿ -M+N) by said CODE NCO MEANS.

64. The method of claim 42, said CODE NCO MEANS comprising a 12-bit ACCUMULATER MEANS, a 12-bit LATCH MEANS, and a MULTIPLEXER MEANS;

wherein said step of providing a clocking signal at C/A code rate and a clocking signal at P code rate for said CODE GENERATOR MEANS by said CODE NCO MEANS further comprises the steps of;

adding on each sample clock edge the output of said LATCH MEANS to the output of said MULTIPLEXER MEANS by said ACCUMULATER;

generating one of three 12-bit values (N,M or SHIFT) by said MULTIPLEXER MEANS;

outputting under normal operation CODE NCO MEANS frequency=10.23 MHz by said CODE NCO MEANS; and

outputting under code phase shift operation code phase shift=(2619-SHIFT)/2500 sample clocks by said CODE NCO MEANS.

65. The method of claim 42, said RESOLVER MEANS comprising a COUNTER MEANS, a COMPARATOR MEANS, and a FLIP-FLOP MEANS, wherein said step of altering the resulting digital delay further comprises the steps of:

clearing said COUNTER MEANS every millisecond on the edge of MSEC signal;

setting the output state of said FLIP-FLOP MEANS to digital 0 every millisecond on the edge of MSEC signal; and

clocking said FLIP-FLOP MEANS by said COMPARATOR MEANS to the output state equal to digital 1 when said COUNTER MEANS reaches a value equal to said COMPARATOR MEANS input value; and

repeating said process every millisecond;

wherein said resulting digital delay=(delay 1+(2500-m)/25000), m being a controllable mark/space ratio; and

wherein said RESOLVER MEANS is used for providing a signal with controllable mark/space ration to toggle between said delay 1 and said delay 2.

66. The method of claim 41;

said L1 TRACKER MEANS comprising a MULTIPLEXER MEANS 1, a CARRIER NCO MEANS 1, a CARRIER MIXER MEANS 1, a CODE GENERATOR MEANS, a CODE MIXER MEANS, a CODE NCO MEANS, a CODE MIXER MEANS 2, a DIGITAL DELAY MEANS 1, a DIGITAL FILTER MEANS 1, a RESOLVER MEANS, and a DIGITAL DELAY MEANS 2;

said L2 comprising a CARRIER NCO MEANS 2, a CARRIER MIXER MEANS 2, a CODE MIXER MEANS 3, a DIGITAL FILTER MEANS 2, a DIGITAL FILTER MEANS 3, a CODE MIXER MEANS 4, and a block CORRELATORS MEANS 2;

wherein said method further comprises the steps of;

locking L1 C/A code tracking loop by said MICROPROCESSOR MEANS;

locking L1 C/A carrier tracking loop by said MICROPROCESSOR MEANS;

computing the L2 carrier frequency aiding term by said MICROPROCESSOR MEANS using the value of L1 frequency;

applying said L2 frequency aiding term to CARRIER NCO MEANS 2;

wherein said L1 and L2 satellite signals are separated in time by ionospheric delay;

adjusting said DIGITAL DELAY MEANS 1 and said DIGITAL DELAY MEANS 2 to compensate for the ionospheric delay between said L1 and said L2 signals until power is found in said L2 CORRELATORS MEANS 2;

locking the L2 carrier tracking loop using said MICROPROCESSOR MEANS; and

locking the L2 code tracking loop using said MICROPROCESSOR MEANS;

whereby the acquisition of the satellite signals L1 and L2 is achieved.

67. The method of claim 66, wherein said method further comprises the steps of:

reading said L1 CORRELATORS MEANS and said L2 CORRELATORS MEANS by said MICROPROCESSOR MEANS;

forming the L1 code tracking loop and applying the output to said CODE NCO MEANS;

forming the L1 carrier tracking loop and applying the output to said CARRIER NCO MEANS 1;

computing the L2 frequency aiding term;

forming the L2 code and carrier tracking loop and applying the output to said DIGITAL DELAY MEANS 1, said DIGITAL DELAY MEANS 2, and said CARRIER NCO MEANS 2;

performing the L1 and L2 carrier phase measurements by reading CARRIER NCO MEANS 1'"'"'s output phase and CARRIER NCO MEANS 2'"'"'s output phase at a chosen MSEC reference time;

performing the L1 and L2 code phase measurements by keeping track in said MICROPROCESSOR MEANS of what shifts have been applied to said CODE NCO MEANS and DIGITAL DELAY MEANS 1 and DIGITAL DELAY MEANS 2 respectively;

whereby the tracking of said satellite signals L1 and a L2 is achieved.

68. A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVING MEANS, said system comprising:

an n-bit RECEIVING MEANS, n being integer, comprising an n-bit A/D CONVERTER for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code-modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite;

wherein said received L1, and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code; and

at least one n-bit DIGITAL CHANNEL PROCESSING MEANS for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;

(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal do not contain propagation noise;

(3) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise;

(4) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(5) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code;

(6) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code; and

(7) correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase;

wherein using said n-bit RECEIVING MEANS comprising an n-bit A/D CONVERTER and each said n-bit DIGITAL CHANNEL PROCESSING MEANS reduces quantization noise as compared to using a one-bit RECEIVING MEANS comprising a one-bit A/D CONVERTER and a one-bit DIGITAL CHANNEL PROCESSING MEANS.

69. A method for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a correlation processing system;

said system comprising an n-bit RECEIVING MEANS and at least one n-bit DIGITAL CHANNEL PROCESSING MEANS, n being an integer;

said method comprising the steps of;

providing said n-bit RECEIVING MEANS comprising an n-bit A/D CONVERTER and each said n-bit DIGITAL CHANNEL PROCESSING MEANS;

receiving a known C/A code modulated on L1 carrier frequency, an unknown Y code modulated on L1 carrier frequency signal, an unknown Y code modulated on L2 carrier frequency signal by said n-bit RECEIVING MEANS;

wherein said received. L1, and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code;

generating local replica of said C/A code modulated on L1 carrier frequency signal by each said DIGITAL CHANNEL PROCESSING MEANS;

generating local replica of said P code modulated on L1 carrier frequency signal by each said DIGITAL CHANNEL PROCESSING MEANS;

wherein said locally generated replica of L1 signal do not contain propagation noise;

extracting of an estimate of said Y code from said L1 signal, and from said L2 signal by said DIGITAL CHANNEL PROCESSING MEANS;

wherein said estimate signals contain propagation noise;

correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

removing said P code from said locally extracted estimate of said L1 Y code by said CHANNEL PROCESSOR to obtain a locally extracted estimate of said L1 W code;

removing said P code from said locally extracted estimate of said L2 Y code by said CHANNEL PROCESSOR to obtain a locally extracted estimate of said L2 W code; and

correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase by said CHANNEL PROCESSOR;

wherein using said n-bit RECEIVING MEANS and said n-bit DIGITAL CHANNEL PROCESSING MEANS reduces quantization noise as compared to using a one-bit RECEIVING MEANS and a one-bit DIGITAL CHANNEL PROCESSING MEANS.