Ferroelectric memory and non-volatile memory cell for same
First Claim
1. A memory cell for a non-volatile integrated circuit memory, said memory cell comprising:
- first transistor means, including a first semiconducting channel region, for effecting transistor action in said first semiconducting channel region to control current flow through said first semiconducting channel region;
ferroelectric transistor means, including a second semiconducting channel region, for effecting transistor action in said second semiconducting channel region to control current flow through said second semiconducting channel region, said ferroelectric transistor means further including a ferroelectric material having a first polarization state and a second polarization state and a ferroelectric gate means for controlling said polarization state of said ferroelectric material; and
second transistor means, including a third semiconducting channel region, for effecting transistor action in said third semiconducting channel region to control current flow through said third semiconducting channel region;
wherein said first, second, and third semiconducting channel regions are connected in series.
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Accused Products
Abstract
A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.
52 Citations
41 Claims
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1. A memory cell for a non-volatile integrated circuit memory, said memory cell comprising:
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first transistor means, including a first semiconducting channel region, for effecting transistor action in said first semiconducting channel region to control current flow through said first semiconducting channel region; ferroelectric transistor means, including a second semiconducting channel region, for effecting transistor action in said second semiconducting channel region to control current flow through said second semiconducting channel region, said ferroelectric transistor means further including a ferroelectric material having a first polarization state and a second polarization state and a ferroelectric gate means for controlling said polarization state of said ferroelectric material; and second transistor means, including a third semiconducting channel region, for effecting transistor action in said third semiconducting channel region to control current flow through said third semiconducting channel region; wherein said first, second, and third semiconducting channel regions are connected in series. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A ferroelectric memory device comprising:
- a substrate, a channel region in said substrate, a first conducting gate overlying at least a first portion of said channel region, a second conducting gate overlying at least a second portion of said channel region, a ferroelectric material overlying at least a third portion of said channel region between said first and second conducting gates, and a ferroelectric gate overlying at least a portion of said ferroelectric material.
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16. A non-volatile integrated circuit memory comprising a plurality of bit lines, a plurality of word lines, a plurality of memory cells, a source of a plate voltage, row address means for applying signals to selected ones of said memory cells via said word lines, column address means for applying signals to selected ones of said memory cells via said bit lines, and data in/out means for applying data signals to and receiving data signals from said memory cells, each memory cell comprising:
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first transistor means, including a first semiconducting channel region, for effecting transistor action in said first semiconducting channel region to control current flow through said first semiconducting channel region; ferroelectric transistor means, including a second semiconducting channel region, for effecting transistor action in said second semiconducting channel region to control current flow through said second semiconducting channel region, said ferroelectric transistor means further including a ferroelectric material capable of existing in a first polarization state and a second polarization state and a ferroelectric gate means for controlling said polarization state of said ferroelectric material; and second transistor means, including a third semiconducting channel region, for effecting transistor action in said third semiconducting channel region to control current flow through said third semiconducting channel region; wherein said first, second, and third semiconducting channel regions are connected in series, each one of said word lines is electrically connected to said first transistor means and said second transistor means in one of said memory cells, said source of a plate voltage is electrically connected to said first semiconducting channel region in each of said memory cells, and each one of said bit lines is electrically connected to said third semiconducting channel in one of said memory cells. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A memory cell for a non-volatile integrated circuit memory, said memory cell comprising:
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a semiconducting substrate; a first doped region formed in said substrate, said doped region including a first portion, a second portion and a third portion connected in series; a first conductor overlying said first portion of said first doped region; a second conductor overlying said third portion of said first doped region; a first insulator between said first conductor and said first portion of said first doped region and a second insulator between said second conductor and said third portion of said first doped region; a ferroelectric member, a first portion of which overlies said first conductor, a second portion of which overlies said second portion of said first doped region, and a third portion of which overlies said second conductor; and a third conductor overlying said ferroelectric member. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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32. A memory cell for a non-volatile integrated circuit memory, said memory cell comprising:
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a first pass gate transistor; a second pass gate transistor; and a ferroelectric transistor electrically connected between said first pass gate transistor and said second pass gate transistor. - View Dependent Claims (33)
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34. A non-volatile integrated circuit memory comprising a plurality of bit lines, a plurality of word lines, a plurality of memory cells, a source of a plate voltage, row address means for applying signals to selected ones of said memory cells via said word lines, column address means for applying signals to selected ones of said memory cells via said bit lines, and data in/out means for applying data signals to and receiving data signals from said memory cells, each memory cell comprising:
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a first pass gate transistor; a second pass gate transistor; and a ferroelectric transistor electrically connected between said first pass gate transistor and said second pass gate transistor; wherein each one of said word lines is electrically connected to said first pass gate transistor and said second pass gate transistor in one of said memory cells, said source of a plate voltage is electrically connected to said first pass gate transistor in each of said memory cells, and each one of said bit lines is electrically connected to said second pass gate transistor in each of said memory cells. - View Dependent Claims (35, 36, 37)
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38. A ferroelectric memory comprising:
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a memory cell including a ferroelectric device having a first logic state and a second logic state; a bit line; a sense amplifier; first connecting means for electrically connecting said ferroelectric device to said bit line; second connecting means for electrically connecting said bit line to said sense amplifier; and timing means connected to said first and second connecting means for;
causing said first connecting means to connect said ferroelectric device to said bit line for a sufficient time to allow said bit line to assume a first voltage determined by the logic state of said ferroelectric device, causing said second connecting means to connect said sense amplifier to said bit line, and causing said first connecting means to disconnect said ferroelectric device from said bit line before said sense amplifier drives said bit line to a second voltage indicative of the logic state of said ferroelectric device. - View Dependent Claims (39, 40, 41)
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Specification