Method and apparatus for storing control information in multi-bit non-volatile memory arrays

• US 5,541,886 A
• Filed: 12/27/1994
• Issued: 07/30/1996
• Est. Priority Date: 12/27/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hasbun, Robert
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/364,307
• Time in Patent Office: 581 Days
• Field of Search: 365/189.01, 365/189.04, 365/189.05, 365/230.03, 365/230.04, 365/230.05, 365/230.06, 365/230.08
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A memory array circuit including a plurality of non-volatile memory cells adapted to selectively store data in either single bit mode or a multi-bit mode, control circuitry for causing control information data to be stored in first preselected ones of the plurality of cells and other data to be stored in other preselected ones of the plurality of cells, and circuitry for accessing the plurality of cells to read, program and erase the cells, the accessing circuitry functioning to access cells for storing control information data in single bit mode and cells for storing other data in either single bit or multi-bit mode.

Claims

1. An apparatus comprising:

a memory array comprising a plurality of nonvolatile memory cells, wherein each cell can store more than one bit of information;

control circuitry for accessing the memory array in a selected one of a multi-bit mode and a single-bit mode, wherein the memory array stores data in one portion of the array and control information for the data in another portion of the array, wherein the control circuitry selects the single-bit mode when accessing the control information, wherein the control circuitry selects one of the single-bit mode and the multi-bit mode when accessing the data.

2. The apparatus of claim 1 wherein the data includes an error detection and correction value.

3. The apparatus of claim 1 wherein the control information includes a cyclic redundancy check value for the data.

4. The apparatus of claim 1 wherein the memory array includes flash electrically-erasable programmable read only memory cells.

5. A memory array comprising:

a plurality of nonvolatile memory cells arranged in separately erasable blocks, each block including an area for storing data and another area for storing control information associated with the data, wherein the nonvolatile memory cells can store more than one bit per cell; and

circuitry for accessing the blocks using logical addresses stored as a part of the control information, wherein the circuitry accesses the control information in a single-bit mode and the circuitry accesses the data in a selected one of a single-bit mode and a multi-bit mode.

6. The memory array of claim 5 wherein the data includes an error detection and correction value.

7. The memory array of claim 5 wherein the control information includes a cyclic redundancy check value.

8. A method of accessing a selected set of data from a plurality of sets of data stored in at least one block of memory, comprising the steps of:

locating a logical address corresponding to a given address, wherein the logical address is located in control information stored in one portion of the block of memory, the memory including a plurality of nonvolatile memory cells, the control information stored in a single-bit per cell mode within the one portion of the block of memory;

accessing control information associated with the logical address in a single-bit per cell mode;

accessing the selected set of data within the block in accordance with the control information associated with the logical address, wherein the selected set of data is accessed in a multi-bit per cell mode.

9. The method of claim 8 further including the step of appending an error detection and correction value to the set of data.

10. The method of claim 8 further including the step of verifying the validity of the control information associated with the logical address by comparing a computed cyclic redundancy check value with a cyclic redundancy check value stored in the control information.