ATM cell assembly and disassembly device with enhanced data handling flexibility

• US 5,541,926 A
• Filed: 10/04/1993
• Issued: 07/30/1996
• Est. Priority Date: 10/02/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Saito, Takeshi, Tsunoda, Keiji, Horiguchi, Akihiro, Suzuki, Muneyuki
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US08/130,136
• Time in Patent Office: 1,030 Days
• Field of Search: 370/94.1, 370/94.2, 370/60.1, 370/99
• US Class Current: 370/474
• CPC Class Codes: H04J 2203/0089 Multiplexing, e.g. coding, scrambling, SONET
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/563 Signalling, e.g. protocols, reference model
• CPC Class Codes: H04L 2012/5636 Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An ATM cell assembly and disassembly device capable of flexibly dealing with various data speeds on STM and ATM sides, and preventing the buffer overflow. In the ATM cell assembly device, the data stored in the buffer are outputted when an amount of the stored data becomes not less than a prescribed data amount sufficient for loading a payload section of each ATM cell, and the ATM cell flow is obtained from the ATM cells assembled from the data outputted from the buffer and empty cells. The buffer can be allowed to output the stored data only when the output permission signal issued in accordance with usage parameter control (UPC) parameters determined at a time of call set up is received. In the ATM cell disassembly device, the output data are stored into the buffer when a currently remaining capacity of the buffer becomes not less than an amount of data loaded in a payload section of each ATM cell, and the STM signals are obtained from the output data outputted from the buffer.

Claims

1. An asynchronous transfer mode (ATM) cell assembly device for obtaining an ATM cell flow by assembling ATM cells from input data, comprising:

buffer means for temporarily storing the input data, from which stored data are outputted when an amount of the stored data becomes not less than a prescribed data amount sufficient for loading a payload section of each ATM cell; and

cell assembly means for assembling each ATM cell by loading the stored data outputted from the buffer means into the payload section and attaching a header section to the payload section, and then for outputting each assembled ATM cell when the stored data outputted from the buffer means are received and for outputting an empty cell when the stored data outputted from the buffer means are not received.

2. The device of claim 1, wherein the input data are entered in forms of synchronous transfer mode (STM) signals formed from a plurality of frames, where each frame is divided into a plurality of time slots, and the device further comprises data input means for extracting selected ones of the time slots in each frame of the STM signals as the input data and storing the extracted input data into the buffer means.

3. The device of claim 1, wherein the input data are entered in forms of synchronous transfer mode (STM) signals formed from continuous bit rate (CBR) signals with an arbitrary speed.

4. The device of claim 1, wherein the buffer means comprises a first-in first-out (FIFO) memory formed by a dual port RAM, to which the input data are stored at operation cycles of an input side from which the input data are entered, and from which the stored data are outputted at operation cycles of an output side to which the ATM cell flow is to be outputted.

5. The device of claim 1, wherein the cell assembly means includes means for generating the empty cells to be outputted when the stored data outputted from the buffer means are not received.

6. The device of claim 1, wherein the cell assembly means includes means for measuring the amount of the stored data in the buffer means at ATM cell output cycles, in accordance with which the cell assembly means acquires the stored data from the buffer means.

7. The device of claim 1, wherein the cell assembly means uses a partial filling scheme and includes dummy pattern output means for generating a dummy pattern to be filled into a remaining portion of a partially filled payload section in each ATM cell after the stored data are loaded.

8. An asynchronous transfer mode (ATM) cell assembly device for obtaining an ATM cell flow by assembling ATM cells from input data, comprising:

encoding means for obtaining the input data by encoding data to be transmitted as the ATM cells;

buffer means for temporarily storing the input data obtained by the encoding means;

output permission means for issuing an output permission signal permitting an output of the input data stored in the buffer means in accordance with usage parameter control (UPC) parameters determined at a time of call set up, where the buffer means is allowed to output the input data stored therein only when the output permission signal is received from the output permission means; and

cell assembly means for assembling each ATM cell by loading the stored input data outputted from the buffer means into a payload section and attaching a header section to the payload section, and outputting the ATM cell flow containing the assembled ATM cells.

9. The device of claim 8, wherein the buffer means controls either one of an encoding speed of the encoding means by which the encoding means encodes the data and an input data output speed of the encoding means by which the encoding means outputs the input data, according to one of an amount of the input data currently stored therein and a buffer capacity currently remaining therein.

10. The device of claim 9, wherein the buffer means controls said one of the encoding speed and the input data output speed of the encoding means such that said one of the encoding speed and the input data output speed of the encoding means is decreased when the amount of the input data currently stored in the buffer means becomes greater than a predetermined threshold, or when the capacity currently remaining in the buffer means becomes less than another predetermined threshold, and said one of the encoding speed and the input data output speed of the encoding means is increased when the amount of the input data currently stored in the buffer means becomes less than said predetermined threshold, or when the capacity currently remaining in the buffer means becomes greater than said another predetermined threshold.

11. The device of claim 8, wherein the buffer means outputs insignificant data different from the input data to be transmitted as said assembled ATM cells when the output permission signal is received from the output permission means when a sufficient amount of the input data are not stored therein, and the cell assembly means outputs one of an empty cell, a signaling cell, and an OAM (Operation, Administration, and Maintenance) cell when the insignificant data are outputted from the buffer means.

12. An asynchronous transfer mode (ATM) cell disassembly device for obtaining output signals from entered ATM cell flow by disassembling ATM cells, comprising:

ATM processing means for extracting output data to be outputted as the output signals from the ATM cells;

buffer means for temporarily storing the output data extracted by the ATM processing means, the output data being supplied from the ATM processing means to the buffer means and stored in the buffer means when a capacity of the buffer means currently remaining becomes not less than an amount of data loaded in a payload section of each ATM cell; and

output processing means for obtaining the output signals from the output data outputted from the buffer means, and outputting the obtained output signals.

13. The device of claim 12, wherein the ATM processing means further comprises:

filter unit for extracting selected ATM cells which have a specific cell header pattern among the ATM cells of the entered ATM cell flow;

jitter absorption buffer unit for temporarily storing at least a part of the selected ATM cells extracted by the filter unit; and

AAL processing unit for extracting the output data from said at least a part of the selected ATM cells stored in the jitter absorption buffer unit and outputting the extracted output data to the buffer means.

14. The device of claim 13, wherein the storing of said at least a part of the selected ATM cells from the filter unit into the jitter absorption buffer unit starts from one of the selected ATM cells whose adaptation layer header has a synchronization bit in an ON state.

15. The device of claim 13, wherein said at least a part of the selected ATM cells are taken out from the jitter absorption buffer unit by the AAL processing unit after an elapse of a prescribed time period since a start of the storing of said at least a part of the selected ATM cells or after a prescribed number of said at least a part of the selected ATM cells are stored from the filter unit to the jitter absorption buffer unit, so as to absorb jitters in cell arrival cycles of the ATM cells.

16. The device of claim 13, wherein the AAL processing unit includes means for measuring the capacity currently remaining in the buffer means at cell arrival cycles of the ATM cells.

17. The device of claim 13, wherein the AAL processing unit includes error recovery means for detecting and correcting cell loss and cell misinsertion errors in the entered ATM cell flow.

18. The device of claim 12, wherein the output signals are synchronous transfer mode (STM) signals formed from a plurality of frames, where each frame is divided into a plurality of time slots, and the output processing means obtains the output signals by loading the output data into the time slots in each frame of the STM signals.

19. The device of claim 12, wherein the STM signals are formed from continuous bit rate (CBR) signals with an arbitrary speed.

20. The device of claim 12, wherein the buffer means comprises a first-in first-out (FIFO) memory formed by a dual port RAM, to which the input data are stored at operation cycles of an input side from which the ATM cell flow is entered, and from which the stored data are outputted at operation cycles of an output side to which the output signals are to be outputted.