Byte aligned communication system for transferring data from one memory to another memory over an ISDN

• US 5,541,930 A
• Filed: 01/10/1995
• Issued: 07/30/1996
• Est. Priority Date: 01/10/1995
• Status: Expired due to Term

• Current Assignee: Edwin E. Klingman
• Original Assignee: Edwin E. Klingman
• Inventors: Klingman, Edwin E.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Patel, Ajit
• Application Number:
  US08/370,965
• Time in Patent Office: 567 Days
• Field of Search: 370/110.1, 370/94.1, 370/79, 370/85.13, 370/105.1, 370/94.3, 370/60, 370/99
• US Class Current: 370/524
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04Q 11/0428 Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/1305 Software aspects
• CPC Class Codes: H04Q 2213/13093 Personal computer, PC
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13174 Data transmission, file transfer
• CPC Class Codes: H04Q 2213/13196 Connection circuit/link/trunk/junction, bridge, router, gateway
• CPC Class Codes: H04Q 2213/13202 Network termination [NT]
• CPC Class Codes: H04Q 2213/13209 ISDN
• CPC Class Codes: H04Q 2213/13216 Code signals, frame structure
• CPC Class Codes: H04Q 2213/1336 Synchronisation

Abstract

A system with source and destination telecommunications transceivers for communicating therebetween over an Integrated Digital Services Network, each having a general purpose computer coupled to an interface circuit for conditioning outgoing and incoming data to and from the communications network. The interface circuit is constructed with a dual port RAM, a subscriber access controller and an ISDN controller. A typical data flow proceeds with the source controller CPU sending bytes of data from a sending buffer in its memory to a first transmit buffer in the dual port RAM. This process continues until the last address in the buffer is filled, whereupon the dual port RAM outputs an interrupt signal to the ISDN controller which responds by sending the data bytes in the buffer to the subscriber access controller for transmission to the ISDN, and sends a control signal instructing the computer to load a second transmit buffer. When the first buffer is emptied the ISDN controller instructs the computer to load the second, etc until all the data is transmitted. When data is being received from the ISDN by the subscriber access controller, it send an interrupt signal to the ISDN controller to hold outgoing data and transfer the incoming data to the computer. The ISDN controller loads the incoming data into one of two receive buffers, and when it is full, sends a signal to the computer to unload the data and proceeds to load the second receive buffer, after which the computer is notified to unload the second buffer. This process is repeated until the incoming data is processed. This process retains byte alignment throughout the interface circuit. In the event that the communications network should require data to be supplied in HDLC frame format, this is provided for by programming in the computer, as is the detection of incoming HDLC framed data and the required extraction of data bytes therefrom.

Claims

1. A communications transceiver for transmitting and receiving data to and from an ISDN comprising:

computer means responsive to a computer interrupt signal for generating a computer address and control signal, and for outputting and receiving data signals in data byte format;

interface circuit means having a receive port and a transmit port for connection to a network termination device to receive and transmit ISDN B-Channel information, said interface circuit means being responsive to said computer address and control signal and operative to receive said data signals in data byte format from said computer means, and to process said data signals without changing their bit organization, and to insert the data signals into the B-Channel of ISDN frames of an ISDN signal format for output via said transmit port to said network termination device, said Interface circuit means being further operative to receive ISDN frames from said network termination device via said receive port and operative to generate said computer interrupt signal and to extract data bytes from the incoming ISDN frames and output said data bytes to said computer means.

2. A communications transceiver system as recited in claim 1 wherein said interface circuit means includes

dual port RAM means responsive to said computer address and control signal and to a first ISDN controller address and control signal and operative in a transmit mode to alternate between loading and storing transmit data bytes from said computer, and unloading the stored transmit data bytes, and further operative in a receive mode to alternate between loading and storing receive data bytes received via said receive port and unload the stored receive data bytes for input to said computer means, and said dual port RAM means being further operative to generate said computer interrupt signal and to generate first ISDN controller interrupt signal.

3. A communications transceiver system as recited in claim 2 wherein said interface circuit means further includes subscriber access controller means responsive in a receive mode to second ISDN address and control signals and to said ISDN frames received via said receive port and operative to extract B channel receive data bytes from said ISDN frames and to generate a second ISDN controller interrupt signal and output said receive data bytes.

4. A communications transceiver system as recited in claim 3 wherein said subscriber access controller means is responsive in a transmit mode to said second ISDN address and control signal, and is operative to receive and inject transmit data bytes into the B-channel of ISDN frames for transmission to an Integrated Services Digital Network via said transmit port.

5. A communications transceiver system as recited in claim 4 wherein said interface circuit means further includes ISDN controller means responsive in a transmit mode to said first ISDN controller interrupt signal and operative to generate said first ISDN address and control signal and said second ISDN address and control signal, said first ISDN address and control signal being operative to cause said dual port RAM means to output said stored transmit data bytes and said computer interrupt signal, said second ISDN address and control signal being operative to cause said subscriber access control means to receive said transmit data bytes.

6. A communications transceiver system as recited in claim 5 wherein said ISDN controller means further includes means responsive in a receive mode to said second ISDN controller interrupt signal and operative to generate said second ISDN address and control signal to cause said subscriber access controller to output said receive data bytes and to generate said first ISDN address and control signal to cause said dual port RAM means to receive said receive data bytes, and to cause said dual port RAM means to generate said computer interrupt signal.

7. A communications transceiver as recited in claim 6 wherein said dual port RAM means includes

transmit buffer means;

first interfacing support circuit means;

second interfacing support circuit means;

third interfacing support circuit means;

fourth interfacing support circuit means;

fifth interfacing support circuit means;

sixth interfacing support circuit means; and

interrupt means;

said transmit buffer means being responsive to said computer address and control signal received via said first interfacing support circuit means and operative to store data bytes received via said second interfacing support circuit means, said interrupt means being responsive to said computer address and control signal and operative to generate an interrupt signal for communication to said ISDN controller via said sixth interfacing support circuit means causing said ISDN controller to generate said first ISDN address and control signal for input to said dual port RAM means via said fourth interfacing support circuit means to cause said transmit buffer means to output stored transmit data bytes to said ISDN controller means via said fifth interfacing support circuit means, and to cause said interrupt means to generate and output said computer interrupt signal via said third interfacing support circuit means to cause said computer means to generate said computer address and control signal and to output said transmit data bytes.

8. A communications transceiver as recited in claim 7 wherein said dual port RAM means further includes receive buffer means responsive to said first ISDN address and control signal received via said fourth interfacing support circuit means and operative to store receive data bytes received via said fifth interfacing support circuit means, and said interrupt means being responsive to said first ISDN address and control signal received via said fourth interfacing support circuit means and operative to generate and output said computer interrupt signal to said computer means via said third interfacing support circuit means to cause said computer means to generate and output said computer address and control signal to said receive buffer means via said first interfacing support circuit means to cause said dual port RAM means to unload and output said received data bytes from said receive buffer means to said computer means via said second interfacing support circuit means.

9. A communications transceiver as recited in claim 6 wherein said ISDN controller means includes

systems control means;

interrupt service means;

first interfacing support circuit means;

second interfacing support circuit means;

third interfacing support circuit means;

fourth interfacing support circuit means;

fifth interfacing support circuit means;

sixth interfacing support circuit means;

wherein, when operating in a transmit mode, said interrupt service means is responsive to said first ISDN controller interrupt signal received via said third interfacing support circuit means and operative to send a first interrupt service control signal to said systems control means to cause said systems control means to output said first ISDN address and control signal via said first interfacing support circuit means to cause said dual port RAM means to output said transmit data bytes and to output said computer interrupt signal, and to cause said system control means to receive said transmit data bytes via said second interfacing support circuit means, and said systems control means to output said second ISDN address and control signal via said fourth interfacing support circuit means to cause said subscriber access controller means to receive said transmit data bytes from said systems control means via said fifth interfacing support circuit means.

10. A communications transceiver as recited in claim 9 wherein, when operating in a receiving mode, said interrupt service means is responsive to said second ISDN controller interrupt signal received via said sixth interfacing support circuit means and operative to output a second interrupt service control signal to said systems control means to cause said systems control means to output said second ISDN address and control signal via said fourth interfacing support circuit means to cause said subscriber access controller means to output said receive data bytes, and to cause said systems control means to receive said receive data bytes via said fifth interfacing support circuit means, and to output said first ISDN address and control signal via said first interfacing support circuit means to cause said dual port RAM means to receive said receive data bytes from said systems control means via said second interfacing support circuit means, and to cause said dual port RAM means to output said computer interrupt signal.

11. A communications transceiver system as recited in claim 1 wherein each said data byte is made up of eight data bits and wherein said computer means further includes

first programming means for inserting the data bits forming the structure of each original data byte into a predetermined format of data bits for making up a data frame of data bytes for outputting to said interface circuit;

and

second programming means for removing said original data bytes from data frames received by said computer means from said interface circuit means.

12. A transceiver system as recited in claim 11 wherein said data frames are High Level Data Link Control frames.

13. A transceiver system as recited in claim 8 wherein

said transmit buffer means includes a first transmit buffer means and a second transmit buffer means, wherein when said ISDN controller is receiving transmit data bytes from one of said first and second transmit buffer means, data bytes from said computer means can be loaded into the other one of said first and second transmit buffer means;

and

said receive buffer means includes a first receive buffer means and a second receive buffer means, wherein when said computer means is receiving receive data bytes from one of said first and second receive buffer means, receive data bytes from said ISDN controller are being loaded into the other one of said first and second receive buffer means.