Circuit for freezing the data in an interface buffer

• US 5,541,932 A
• Filed: 02/03/1995
• Issued: 07/30/1996
• Est. Priority Date: 06/13/1994
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Nguyen, Uoc H., Su, Sam, Cheung, Li-Fung, Apostol, George
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): VU, HUY DUY
• Application Number:
  US08/383,032
• Time in Patent Office: 543 Days
• Field of Search: 370/85.1, 370/85.2, 370/85.6, 370/85.7, 370/85.9, 370/85.11, 370/85.13, 340/825.15, 340/825.5, 364/DIG. 1, 395/280, 395/306, 395/308, 395/309, 395/872, 395/875
• US Class Current: 370/462
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.

Claims

1. A circuit for allowing the transfer of data between first and second data busses, comprising:

a first buffer for coupling packets from said second bus to said first bus, and for generating an empty signal,

a second buffer for coupling packets from said first bus to said second bus, and for generating a full signal,

a source device for transmitting packets of data to said second bus and for generating a source data request signal when said source device requires that data be output,

a destination device for receiving packets of data from said second bus and for generating a destination data request signal when said destination device requires data to be input,

means for generating a freeze signal for each device,

first logic means for receiving said source data request signal, said buffer empty signal and said source device freeze signal, and for generating a first output signal therefrom only if said source device freeze signal is inactive,

second logic means for receiving said destination data request signal, said buffer full signal and said destination device freeze signal, and for generating a second output signal therefrom only if said destination device freeze signal is inactive, and

an arbitrator responsive to said first and second output signals for generating an enabling signal for enabling either a transfer of data from said source device to said first buffer or a transfer of data to from said second buffer to said destination device, said arbitrator being further adapted to allow the completion of the transfer of a packet of data when said enabling signal is interrupted by a freeze signal during the transmission of a packet.