Integrated circuit with test signal buses and test control circuits

• US 5,541,935 A
• Filed: 05/26/1995
• Issued: 07/30/1996
• Est. Priority Date: 05/26/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Waterson, Kent B.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/450,726
• Time in Patent Office: 431 Days
• Field of Search: 395/183.03, 395/183.06, 371/22.5, 371/22.3, 371/22.6, 371/27
• US Class Current: 714/733
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

An integrated circuit (IC) with multiple input-only, output-only and combination input/output terminals which can be functionally tested at both the IC and circuit board levels includes programmably-designated, internal test signal buses for allowing functional tests to be performed upon portions of the IC not normally accessible via its outside terminals. Programmably-controlled signal switches allow input and output test signals to be routed directly to and from those functional areas of the IC sought to be tested. Further included are a logic circuit for logically ANDing all of the input signals and programmably-controlled output signal buffers for selectively driving each output terminal to a logic zero, logic one or high impedance state, thereby allowing tests to be conducted to ensure that the various input and output terminals are not electrically shorted to one another or circuit ground.

Claims

1. An apparatus including an integrated circuit (IC) with a plurality of test signal buses for use in performing a plurality of internal logic tests, said IC comprising:

a plurality of signal terminals for inputting a plurality of input signals and outputting a plurality of output signals;

a first plurality of logic circuits for inputting a first plurality of logic signals and outputting a second plurality of logic signals;

a second plurality of logic circuits, coupled to said plurality of signal terminals, for providing a first plurality of internal signals and receiving a second plurality of internal signals;

a first test signal bus, coupled to a portion of said plurality of signal terminals, for receiving a first plurality of test signals therefrom;

a first plurality of signal switches, coupled between said first test signal bus and said first plurality of logic circuits, for receiving said first plurality of internal signals and for receiving a first plurality of control signals and in accordance therewith communicating either said first plurality of internal signals or said first plurality of test signals to said first plurality of logic circuits as said first plurality of logic signals;

a second test signal bus, coupled to another portion of said plurality of signal terminals, for providing a second plurality of test signals thereto; and

a second plurality of signal switches, coupled between said first plurality of logic circuits and said second test signal bus, for receiving a second plurality of control signals and in accordance therewith communicating said second plurality of logic signals either to said second test signal bus as said second plurality of test signals or to said second plurality of logic circuits as said second plurality of internal signals.

2. The apparatus of claim 1, wherein said plurality of input signal switches comprises a plurality of multiplexors.

3. The apparatus of claim 1, wherein said plurality of output signal switches comprises a plurality of tri-state buffers.

4. The apparatus of claim 1, wherein said plurality of output signal switches comprises a plurality of demultiplexors.

5. The apparatus of claim 1, further comprising a test controller for receiving a plurality of test control signals and in accordance therewith providing said first and second pluralities of control signals.

6. The apparatus of claim 5, wherein said plurality of test control signals comprises a test mode enablement signal and a plurality of programmable test mode select signals.

7. An apparatus including an integrated circuit (IC) with a plurality of test control circuits for use in performing a plurality of external logic tests, said IC comprising:

a first plurality of signal terminals for inputting a first plurality of input signals;

a second plurality of signal terminals for outputting a first plurality of output signals;

a third plurality of signal terminals for selectively inputting a second plurality of input signals and outputting a second plurality of output signals;

a first plurality of output drivers, coupled to said second plurality of signal terminals, for receiving a first plurality of control signals and in accordance therewith providing said first plurality of output signals, wherein each one of said first plurality of output signals is set to one of a plurality of logic states in accordance with said first plurality of control signals;

a second plurality of output drivers, coupled to said third plurality of signal terminals, for receiving a second plurality of control signals and in accordance therewith providing said second plurality of output signals, wherein each one of said second plurality of output signals is set to one of a plurality of logic states in accordance with said second plurality of control signals; and

a logic circuit, coupled to said first and third pluralities of signal terminals, for receiving said first and second pluralities of input signals and in accordance therewith providing an input status signal representing a logic status of said first and second pluralities of input signals.

8. The apparatus of claim 7, wherein each one of said first plurality of output signals is set to a logic zero, logic one or high impedance state in accordance with said first plurality of control signals.

9. The apparatus of claim 7, wherein each one of said second plurality of output signals is set to a logic zero, logic one or high impedance state in accordance with said second plurality of control signals.

10. The apparatus of claim 7, wherein said logic circuit comprises an AND gate.

11. An apparatus including an integrated circuit (IC) with a plurality of test signal buses and a plurality of test control circuits for use in performing pluralities of internal and external logic tests, said IC comprising:

a first plurality of signal terminals for inputting a first plurality of input signals;

a second plurality of signal terminals for outputting a first plurality of output signals;

a third plurality of signal terminals for selectively inputting a second plurality of input signals and outputting a second plurality of output signals;

a first plurality of logic circuits for inputting a first plurality of logic signals and outputting a second plurality of logic signals;

a second plurality of logic circuits, coupled to said first, second and third pluralities of signal terminals, for providing a first plurality of internal signals and receiving a second plurality of internal signals;

a first test signal bus, coupled to said first and third pluralities of signal terminals, for receiving a first plurality of test signals therefrom;

a first plurality of signal switches, coupled between said first test signal bus and said first plurality of logic circuits, for receiving said first plurality of internal signals and for receiving a first plurality of control signals and in accordance therewith communicating either said first plurality of internal signals or said first plurality of test signals to said first plurality of logic circuits as said first plurality of logic signals;

a second test signal bus, coupled to said second and third pluralities of signal terminals, for providing a second plurality of test signals thereto;

a second plurality of signal switches, coupled between said first plurality of logic circuits and said second test signal bus, for receiving a second plurality of control signals and in accordance therewith communicating said second plurality of logic signals either to said second test signal bus as said second plurality of test signals or to said second plurality of logic circuits as said second plurality of internal signals;

a first plurality of output drivers, coupled to said second plurality of signal terminals, for receiving a third plurality of control signals and in accordance therewith providing said first plurality of output signals, wherein each one of said first plurality of output signals is set to one of a plurality of logic states in accordance with said third plurality of control signals;

a second plurality of output drivers, coupled to said third plurality of signal terminals, for receiving a fourth plurality of control signals and in accordance therewith providing said second plurality of output signals, wherein each one of said second plurality of output signals is set to one of a plurality of logic states in accordance with said fourth plurality of control signals; and

a logic circuit coupled to said first and third pluralities of signal terminals, for receiving said first and second pluralities of input signals and in accordance therewith providing an input status signal representing a logic status of said first and second pluralities of input signals.

12. The apparatus of claim 11, wherein said plurality of input signal switches comprises a plurality of multiplexors.

13. The apparatus of claim 11, wherein said plurality of output signal switches comprises a plurality of tri-state buffers.

14. The apparatus of claim 11, wherein said plurality of output signal switches comprises a plurality of demultiplexors.

15. The apparatus of claim 11, further comprising a test controller for receiving a plurality of test control signals and in accordance therewith providing said first and second pluralities of control signals.

16. The apparatus of claim 14, wherein said plurality of test control signals comprises a test mode enablement signal and a plurality of programmable test mode select signals.

17. The apparatus of claim 11, wherein each one of said first plurality of output signals is set to a logic zero, logic one or high impedance state in accordance with said first plurality of control signals.

18. The apparatus of claim 11, wherein each one of said second plurality of output signals is set to a logic zero, logic one or high impedance state in accordance with said second plurality of control signals.

19. The apparatus of claim 11, wherein said logic circuit comprises an AND gate.