Adaptive data rate modem

• US 5,541,955 A
• Filed: 04/28/1995
• Issued: 07/30/1996
• Est. Priority Date: 11/06/1992
• Status: Expired due to Term

• Current Assignee: Pericle Wireless Technology, Inc.
• Original Assignee: Pericle Communications Company
• Inventors: Jacobsmeyer, Jay M.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): PHAN, HAI
• Application Number:
  US08/430,268
• Time in Patent Office: 459 Days
• Field of Search: 375/222, 375/219, 375/221, 375/261, 375/262, 375/265, 375/340, 375/341, 375/371-376, 375/377, 371/43
• US Class Current: 375/222
• CPC Class Codes: H03D 3/241 the oscillator being part of a phase locked loop
• CPC Class Codes: H03K 7/04 Position modulation, i.e. PPM
• CPC Class Codes: H04L 1/0007 by modifying the frame length
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0015 characterised by the adaptation strategy
• CPC Class Codes: H04L 1/0021 in which the algorithm uses adaptive thresholds
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 27/0008 arrangements for allowing a transmitter or receiver to use more than one type of modulation negotiating modulation type for two-way transmission paths H04L5/1453
• CPC Class Codes: H04L 5/1446 of transmission speed
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An adaptive data rate modulator/demodulator (modem) (102), particularly useful for transmitting data over fading communications channels, uses an adaptive data rate technique which supports multiple data rates in the same device. The modem incorporates an adaptive data rate encoder (104) and an adaptive data rate decoder (105) using adaptive, parallel-branch decoding to translate received symbols into corresponding data bits. Significantly, the soft decision metrics of the decoder are also used to provide an estimate W of the signal-to-noise ratio. An optional predictor (232) receives W from the adaptive data rate decoder (105) and predicts the future signal-to-noise ratio to determine the desired data rate for the modem. The data rate is changed automatically and dynamically without interrupting the decoding process. A constant channel symbol rate and a single signal set simplify signal acquisition and synchronization. Incoming and outgoing data are buffered, and the transmission rate is changed dynamically by a memory controller (109) to avert buffer overflows and underflows. An optional adaptive phase-lock loop system (116) maintains synchronization of the decoder at all data rates.

Claims

1. A modem operating at one of a plurality of data rates for use with a forward channel transmitter, a forward channel receiver, a return channel transmitter, and a return channel receiver, comprising:

a. encoding means for generating l output bits as a function of j input bits, where l is greater than j;

b. mapping means connected to said encoding means for mapping the l-bit output of said encoding means to an element of a predetermined symbol set for transmission by said forward channel transmitter over a forward channel to said forward channel receiver; and

c. trellis decoder means connected to said forward channel receiver for searching a trellis, for selecting a trellis path which most closely resembles the received symbol sequence in terms of a cumulative path metric, for providing a decoded bit sequence as an output in response to the selected trellis path and the number of data bits per symbol in each branch of the selected trellis path, for estimating a reliable data rate as a function of a cumulative path metric of at least one survivor path, for dynamically and without interruption searching a dynamically changing trellis, and wherein the number of bits per symbol is dynamically changing; and

d. said trellis decoder means connected to said return channel transmitter for transmitting data rate information to said return channel receiver for use, in real time, by at least one of said encoding means and said mapping means.

2. The modem of claim 1 wherein the symbols are transmitted at a constant rate.

3. The modem of claim 1, wherein said encoding means comprises an encoder with i coded input bits, where i is less than or equal to j, and j minus i uncoded bits connected directly to said mapper, whereby a trellis structure is constructed with parallel branches between trellis states.

4. The modem of claim 1 wherein said trellis decoder means adjusts the data rate dynamically and without interruption.

5. The modem of claim 1, further comprising predictor means connected to said trellis decoding means and connected to a return channel for predicting future reliable data rates.

6. The modem of claim 1 further comprising adaptive data transfer means for transferring data between a memory and said encoding means at a dynamically selected one of a plurality of data rates.

7. The modem of claim 6 wherein said adaptive data transfer means comprises:

a. a first shift register of size J bits where J is a common multiple of the data rates in bits per symbol;

b. a second shift register of size k bits where k is the highest data rate in bits per symbol;

c. a first counter, modulo-k with a variable start, for counting from k minus K_i to k bits where K_i is one of a plurality of data rates, and where K_i is less than or equal to k;

d. a second counter, modulo J-1, for counting from 0 to J-1;

e. said first shift register connected to said second shift register through a serial data line, to said first counter through a shift control line, to said second counter through a load line and said shift control line, and to an external memory through a data bus of size J bits;

f. said second shift register being connected to said shift control line and further having k output bits from said second shift register connected to an output;

g. said first counter being connected to a NAND gate through said first counter'"'"'s output line, to an external load pulse signal, an external bit clock, and an external data rate word; and

h. said second counter being connected to said shift control line at said second counter'"'"'s clock input and to an external memory read line through said second counter'"'"'s output line.

8. The modem of claim 1, further comprising a memory controller, having:

a. storage means having limited storage capacity for storing an amount of incoming digital information for delivery to the encoding means;

b. monitoring means connected to said storage means for monitoring the amount of information stored in said storage means and producing control signals based on said amount;

c. control means for controlling the amount of information stored in said storage means by raising the system data rate in response to said control signals when said control signals indicate that overflow of said storage means is imminent and by lowering the system data rate in response to said control signals when said control signals indicate that underflow of said storage means is imminent.

9. The modem of claim 8 wherein said control means controls the occurrence of data rate changes by adjusting rate changing thresholds of the modem as a function of said amount of information stored, whereby the throughput is increased or decreased thereby reducing the need for rate changes to preclude overflow or underflow of the storage means.

10. The modem of claim 8 where said control means raises the system data rate when said amount of information stored exceeds a threshold, NMAX, and lowers the system data rate when said amount of information stored is less than a second threshold, NMIN.

11. The modem of claim 10 wherein said control means further controls the occurrence of data rate changes by adjusting rate changing thresholds of the modem as a function of said amount of information stored, whereby the throughput is increased or decreased thereby reducing the need for rate changes to preclude overflow or underflow of the storage means.

12. The modem of claim 1 further comprising an adaptive phase locked loop receiving data from said forward channel receiver for achieving synchronization at any of a set of predefined data rates.

13. The modem of claim 12 wherein said adaptive phase locked loop comprises:

a. a bandpass filter having an input connected to receive data from said forward channel receiver and having an output;

b. a programmable M^th power law device having an input connected to receive the output of said bandpass filter and producing an output therefrom corresponding to the input raised to the M^th power;

c. phase detecting means having a first input connected to the output of said M^th power law device and also having an output representing the phase error of the input;

d. a programmable loop filter having an input connected to the output of said phase detecting means and also having an output representing a filtered version of the input;

e. a programmable voltage controlled oscillator having an input connected to the output of said programmable loop filter and having an output connected as a second input to said phase detecting means;

f. a programmable divide-by-M circuit connected to the output of said programmable voltage controlled oscillator providing an output to a demodulator; and

g. variation means for selecting the value of M and for modifying operating parameters of said programmable loop filter and said voltage controlled oscillator based on the value of said data rate of said received data.

14. A modem operating at one of a plurality of data rates for use with a forward channel transmitter, a forward channel receiver, a return channel transmitter, and a return channel receiver, comprising:

a. encoding means for generating l output bits as a function of j input bits, where l is greater than j;

b. mapping means connected to said encoding means for mapping the l-bit output of said encoding means to an element of a predetermined symbol set for transmission by said forward channel transmitter over a forward channel to said forward channel receiver; and

c. trellis decoder means connected to said forward channel receiver for searching a trellis, for selecting a trellis path which most closely resembles the received symbol sequence in terms of a cumulative path metric, for providing a decoded bit sequence as an output in response to the selected trellis path and the number of data bits per symbol in each branch of the selected trellis paths, for dynamically and without interruption searching a dynamically changing trellis, and wherein the number of bits per symbol is dynamically changing; and

d. estimation means connected to said trellis decoder means for estimating a reliable data rate based on channel conditions, said estimation means also connected to said return channel transmitter for transmission over a return channel, for reception by said return channel receiver, and for use, in real time, by said at least one of said encoding means and said mapping means for determining a reliable data rate.

15. The modem of claim 14 wherein the symbols are transmitted at a constant rate.

16. The modem of claim 14, wherein said encoding means comprises an encoder with i coded input bits, where i is less than or equal to j, and j minus i uncoded bits connected directly to said mapper, whereby a trellis structure is constructed with parallel branches between trellis states.

17. The modem of claim 14 wherein said trellis decoder means adjusts the data rate dynamically and without interruption.

18. The modem of claim 14 wherein said estimation means generates an estimate of said reliable data rate as a function of said cumulative path metric.

19. The modem of claim 14 wherein said estimation means compares a minimum distance path with the path with the next largest accumulated metric and when the difference between the two paths is greater than a predetermined number, directs an increase in data rate and when the difference between the said two paths is less than a predetermined number, directs one of a reduction in data rate and a cessation of data transmission.

20. The modem of claim 14, wherein said estimation means includes means for performing least mean square estimation of said reliable data rate.

21. The modem of claim 14, further comprising predictor means connected to said estimation means and connected to a return channel for predicting future reliable data rates.

22. The modem of claim 14 further comprising adaptive data transfer means for transferring data between a memory and said encoding means at a dynamically selected one of a plurality of data rates.

23. The modem of claim 22 wherein said adaptive data transfer means comprises:

a. a first shift register of size J bits where J is a common multiple of the data rates in bits per symbol;

b. a second shift register of size k bits where k is the highest data rate in bits per symbol;

c. a first counter, modulo-k with a variable start, for counting from k minus K_i to k bits where K_i is one of a plurality of data rates, and where K_i is less than or equal to k;

d. a second counter, modulo J-1, for counting from 0 to J-1;

e. said first shift register connected to said second shift register through a serial data line, to said first counter through a shift control line, to said second counter through a load line and said shift control line, and to an external memory through a data bus of size J bits;

f. said second shift register being connected to said shift control line and further having k output bits from said second shift register connected to an output;

g. said first counter being connected to a NAND gate through said first counter'"'"'s output line, to an external load pulse signal, an external bit clock, and an external data rate word, and

h. said second counter being connected to said shift control line at said second counter'"'"'s clock input and to an external memory read line through said second counter'"'"'s output line.

24. The modem of claim 14, further comprising a memory controller, having:

a. storage means having limited storage capacity for storing an amount of incoming digital information for delivery to said encoding means;

b. monitoring means connected to said storage means for monitoring the amount of information stored in said storage means and producing control signals based on said amount;

c. control means for controlling the amount of information stored in said storage means by raising the system data rate in response to said control signals when said control signals indicate that overflow of said storage means is imminent and by lowering the system data rate in response to said control signals when said control signals indicate that underflow of said storage means is imminent.

25. The modem of claim 24 wherein said control means controls the occurrence of data rate changes by adjusting rate changing thresholds of the modem as a function of said amount of information stored, whereby the throughput is increased or decreased thereby reducing the need for rate changes to preclude overflow or underflow of said storage means.

26. The modem of claim 24 where said control means raises the system data rate when said amount of information stored exceeds a threshold, NMAX, and lowers the system data rate when said amount of information stored is less than a second threshold, NMIN.

27. The modem of claim 26 wherein said control means further controls the occurrence of data rate changes by adjusting rate changing thresholds of the modem as a function of said amount of information stored, whereby the throughput is increased or decreased thereby reducing the need for rate changes to preclude overflow or underflow of said storage means.

28. The modem of claim 14 further comprising an adaptive phase locked loop for receiving data from said forward channel receiver for achieving synchronization at any of a set of predefined data rates.

29. The modem of claim 28 wherein said adaptive phase locked loop comprises:

a. a bandpass filter having an input connected to receive data from said forward channel receiver and having an output;

b. a programmable M^th power law device having an input connected to receive the output of said bandpass filter and producing an output therefrom corresponding to the input raised to the M^th power;

c. phase detecting means having a first input connected to the output of said M^th power law device and also having an output representing the phase error of the input;

d. a programmable loop filter having an input connected to the output of said phase detecting means and also having an output representing a filtered version of the input;

e. a programmable voltage controlled oscillator having an input connected to the output of said programmable loop filter and having an output connected as a second input to said phase detecting means;

f. a programmable divide-by-M circuit connected to the output of said programmable voltage controlled oscillator providing an output to a demodulator, and

g. variation means for selecting the value of M and for modifying operating parameters of said programmable loop filter and said voltage controlled oscillator based on the value of said data rate of said received data.

30. An electrical circuit for transferring data at one of a plurality of data rates comprising:

a. a first shift register of size J bits where J is a common multiple of the data rates in bits per symbol;

b. a second shift register of size k bits where k is the highest data rate in bits per symbol;

c. a first counter, modulo-k with a variable start, for counting from k minus K_i to k bits where K_i is one of a plurality of data rates, and where K_i is less than or equal to k;

d. a second counter, modulo J-1, for counting from 0 to J-1;

e. said first shift register connected to said second shift register through a serial data line, to said first counter through a shift control line, to said second counter through a load line and said shift control line, and to an external memory through a data bus of size J bits;

f. said second shift register being connected to said shift control line and further having k output bits from said second shift register connected to an output;

g. said first counter being connected to a NAND gate through said first counter'"'"'s output line, to an external load pulse signal, an external bit clock, and an external data rate word, and

h. said second counter being connected to said shift control line at said second counter'"'"'s clock input and to an external memory read line through said second counter'"'"'s output line.

31. An adaptive phase-locked loop comprising:

a. a bandpass filter having an input connected to receive data from said forward channel receiver and having an output;

b. a programmable M^th power law device having an input connected to receive the output of said bandpass filter and producing an output therefrom corresponding to the input raised to the M^th power;

c. phase detecting means having a first input connected to the output of said M^th power law device and also having an output representing the phase error of the input;

d. a programmable loop filter having an input connected to the output of said phase detecting means and also having an output representing a filtered version of the input;

e. a programmable voltage controlled oscillator having an input connected to the output of said programmable loop filter and having an output connected as a second input to said phase detecting means;

f. a programmable divide-by-M circuit connected to the output of said programmable voltage controlled oscillator providing an output to a demodulator; and

g. variation means for selecting the value of M and for modifying operating parameters of said programmable loop filter and said voltage controlled oscillator based on the value of said data rate of said received data.

32. A method for transmitting and receiving data over a two-way communications channel at one of a plurality of data rates, comprising the steps of:

a. encoding data by mapping J output bits to l output bits, where l is greater than j;

b. mapping said l output bits to an element S_jk '"'"', of a predetermined symbol set by dynamically and without interruption searching a dynamically changing trellis, wherein the number of bits per symbol is dynamically changing;

c. transmitting said element over a forward channel;

d. receiving said element and generating an estimate, S_jk '"'"', i=1, 2, . . . , in terms of a predetermined metric;

f. providing a decoded bit sequence as an output in response to selected trellis path and the number of data bits per symbol in the selected trellis path;

g. estimating a reliable data rate based on channel conditions;

h. transmitting data rate information over a return channel; and

i. receiving said data rate information for use, in real time, by said encoding step for determining an operating data rate.

33. A system for transmitting and receiving data over a communications channel, comprising:

a. encoding means for mapping data to elements of a predefined symbol alphabet having symbol alphabet elements by dynamically and without interruption searching a dynamically changing trellis, and wherein the number of bits per symbol is dynamically changing;

b. transmitting means connected to the encoding means for transmitting signals representative of the symbol alphabet elements over the communications channel at one of a set of predefined data rates;

c. receiving means for receiving signals representative of elements of the symbol alphabet over the communications channel and producing in accordance therewith signals representative of the received symbol alphabet elements;

d. decoding means connected to the receiving means for receiving said representative signals and generating in response thereto received data signals representative of the signals received;

e. predictor means connected to said decoding means for estimating and having an output predicting future reliable data rates based on channel conditions, and

f. means for sending said predictor means output to the transmitting means to control the selection of said data rate thereof, in real time, in response to the predictor means output.

34. A method for transmitting and receiving data over a communications channel, comprising the steps of:

a. encoding data to be transmitted by mapping said data to elements of a predefined symbol alphabet having symbol alphabet elements for dynamically and without interruption searching a dynamically changing trellis, and wherein the number of bits per symbol is dynamically changing;

b. transmitting signals representative of said symbol alphabet elements over the communications channel at one of a set of predefined data transmission rates;

c. receiving signals representative of elements of the symbol alphabet over the communications channel;

d. decoding said signals and generating in response thereto received data signals representative of the signals received;

e. predicting future reliable data rates based on channel conditions;

f. controlling said data transmission rate during the transmission in real time in response to the prediction of future reliable data rates.

35. A modem operating at one of a plurality of data rates for use with a forward channel transmitter, a forward channel receiver, a return channel transmitter, and a return channel receiver, comprising:

a. encoding means for generating l output bits as a function of j input bits, where l is greater than j;

b. mapping means connected to said encoding means for mapping the l-bit output of said encoding means to an element of a predetermined symbol set for transmission by said forward channel transmitter over a forward channel to said forward channel receiver for dynamically and without interruption searching a dynamically changing trellis, and wherein the number of bits per symbol is dynamically changing; and

c. trellis decoder means connected to said forward channel receiver for dynamically and without interruption searching a dynamically changing trellis, for selecting a trellis path which most closely resembles the received symbol sequence in terms of a cumulative path metric, for providing a decoded bit sequence as an output in response to the selected trellis path and the number of data bits per symbol in each branch of the selected trellis path, and for estimating a reliable data rate as a function of a cumulative path metric of at least one survivor path; and

d. said trellis decoder means connected to said return channel transmitter for transmitting data rate information to said return channel receiver for use in real time with at least one of said encoding means and said mapping means.

36. The modem of claim 35 wherein the symbols are transmitted at a constant rate.

37. The modem of claim 35, wherein said encoding means comprises an encoder with i coded input bits, where i is less than or equal to j, and j minus i uncoded bits connected directly to said mapper, whereby a trellis structure is constructed with parallel branches between trellis states.

38. The modem of claim 35, further comprising predictor means connected to said trellis decoder means and connected to a return channel for predicting future reliable data rates.

39. The modem of claim 35 further comprising adaptive data transfer means for transferring data between a memory and said encoding means at a dynamically selected one of a plurality of data rates.

40. The modem of claim 39 wherein said adaptive data transfer means comprises:

a. a first shift register of size J bits where J is a common multiple of the data rates in bits per symbol;

b. a second shift register of size k bits where k is the highest data rate in bits per symbol;

c. a first counter, modulo-k with a variable start, for counting from k minus K_i to k bits where K_i is one of a plurality of data rates, and where K_i is less than or equal to k;

d. a second counter, modulo J-1, for counting from 0 to J-1;

e. said first shift register connected to said second shift register through a serial data line, to said first counter through a shift control line, to said second counter through a load line and said shift control line, and to an external memory through a data bus of size J bits;

f. said second shift register being connected to said shift control line and further having k output bits from said second shift register connected to an output;

g. said first counter being connected to a NAND gate through said first counter'"'"'s output line, to an external load pulse signal, an external bit clock, and an external data rate word; and

h. said second counter being connected to said shift control line at said second counter'"'"'s clock input and to an external memory read line through said second counter'"'"'s output line.

41. The modem of claim 35, further comprising a memory controller, having:

a. storage means having limited storage capacity for storing an amount of incoming digital information for delivery to the forward channel transmitter;

b. monitoring means connected to said storage means for monitoring the amount of information stored in said storage means and producing control signals based on said amount;

c. control means for controlling the amount of information stored in said storage means by raising the system data rate in response to said control signals when said control signals indicate that overflow of said storage means is imminent and by lowering the system data rate in response to said control signals when said control signals indicate that underflow of said storage means is imminent.

42. The modem of claim 41 wherein said control means controls the occurrence of data rate changes by adjusting rate changing thresholds of the modem as a function of said amount of information stored, whereby the throughput is increased or decreased thereby reducing the need for rate changes to preclude overflow or underflow of said storage means.

43. The modem of claim 41 where said control means raises the system data rate when said amount of information stored exceeds a threshold, NMAX, and lowers the system data rate when said amount of information stored is less than a second threshold, NMIN.

44. The modem of claim 43 wherein said control means further controls the occurrence of data rate changes by adjusting rate changing thresholds of the modem as a function of said amount of information stored, whereby the throughput is increased or decreased thereby reducing the need for rate changes to preclude overflow or underflow of said storage means.

45. The modem of claim 35 further comprising an adaptive phase locked loop for receiving data from said forward channel receiver for achieving synchronization at any of a set of predefined data rates.

46. The modem of claim 45 wherein said adaptive phase locked loop comprises:

a. a bandpass filter having an input connected to receive data from said forward channel receiver and having an output;

b. a programmable M^th power law device having an input connected to receive the output of said bandpass filter and producing an output therefrom corresponding to the input raised to the M^th power;

c. phase detecting means having a first input connected to the output of said M^th power law device and also having an output representing the phase error of the input;

d. a programmable loop filter having an input connected to the output of said phase detecting means and also having an output representing a filtered version of the input;

e. a programmable voltage controlled oscillator having an input connected to the output of said programmable loop filter and having an output connected as a second input to said phase detecting means;

f. a programmable divide-by-M circuit connected to the output of said programmable voltage controlled oscillator providing an output to a demodulator; and

g. variation means for selecting the value of M and for modifying operating parameters of said programmable loop filter and said voltage controlled oscillator based on the value of said data rate of the received data.