Artificial neurons using delta-sigma modulation

• US 5,542,054 A
• Filed: 12/22/1993
• Issued: 07/30/1996
• Est. Priority Date: 12/22/1993
• Status: Expired due to Fees

• Current Assignee: George W. Batten Jr
• Original Assignee: George W. Batten Jr
• Inventors: Batten, George W. Jr.
• Primary Examiner(s): Davis, George B.
• Application Number:
  US08/173,566
• Time in Patent Office: 951 Days
• Field of Search: 395/24, 395/27, 395/22, 307/201
• US Class Current: 706/26
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

An artificial neuron for use in a neural processing network comprises a plurality of input signal lines, an arrangement for computing a nonlinear function of the sum of the inputs multiplied by associated weights, and a saturating delta-sigma modulator which oversamples the computed value and produces an encoded neuron output signal. Conversion of signals for use by these neurons preferably is performed by delta-sigma modulators at the inputs to the neurons, which may be incorporated directly into sensors. Processing of the output signals from the neuron includes low-pass filtering and decimation. The present invention may be used in many diverse areas. For example, arrays of sensors with delta signal modulators may be coupled with a network of the neurons to form an intelligent vision system. Linear signal processing, both conventional and adaptive, can be done by a simple neuronal system that operates linearly.

Claims

1. A neuron comprising:

a plurality of input lines for providing a plurality of input signals to said neuron;

a neuron input unit receiving said input signals and outputting an intermediate signal;

a delta sigma modulator Which includes a saturating adder, said delta sigma modulator receiving said intermediate signal from said neuron input unit and producing a neuron output signal in response.

2. A neuron as in claim 1, wherein said plurality of input signals are analog signals.

3. A neuron as in claim 2 further comprising a delta sigma modulator connected to at least one of said plurality of input lines.

4. A neuron as in claim 1, wherein said plurality of input signals are two-state signals.

5. A neuron as in claim 4, wherein the two-states are 1 and -1.

6. A neuron as in claim 1, wherein each of the plurality of input signals is a digital signal.

7. A neuron as in claim 1, wherein at least one of the plurality of input signals is an analog signal.

8. A neuron as in claim 1, wherein the neuron output signal is applied as an input to another neuron.

9. A neuron as in claim 1, wherein the delta sigma modulator has a sampling rate f_s, and the intermediate signal has a maximum frequency f_o, and the sampling rate f_s of the delta sigma modulator is greater than twice the maximum frequency f_o of the intermediate signal.

10. A neuron as in claim 1, wherein each of the plurality of input signals comprise a multibit signal.

11. A neuron as in claim 1, wherein the neuron output signal comprises a multibit signal.

12. A neuron as in claim 1, wherein said neuron input unit applies a transfer function to said input signals, and said transfer function is defined by instructions stored in a memory unit.

13. A neuron as in claim 1, wherein said neuron input unit comprises a memory unit.

14. A neuron as in claim 13, wherein the plurality of input signals form an address into the memory unit to a word, and the word stored at said address comprises the intermediate signal.

15. A neuron as in claim 13, wherein the delta sigma modulator comprises a latch receiving the intermediate signal and producing an output signal that comprises the neuron output signal in response to the clock pulse.

16. A neuron as in claim 15, wherein only the most significant digit of the latch output signal comprises the neuron output signal.

17. A neuron as in claim 16, wherein the latch output signal is applied as an input to the memory unit.

18. A neuron as in claim 1, wherein the delta sigma modulator operates in an analog domain.

19. A neuron as in claim 1, wherein the neuron is embodied in an integrated circuit.

20. A device as in claim 1, wherein said neuron forms part of a neural processing network.

21. A device as in claim 20, wherein said neural processing network includes a plurality of delta sigma neurons.

22. A device as in claim 21, wherein said neural processing network includes a low pass filter which provides a network output.

23. A neuron comprising:

a plurality of input lines for providing a plurality of input signals to said neuron;

a neuron input unit receiving said input signals and outputting an intermediate signal;

a delta sigma modulator receiving said intermediate signal from said neuron input unit and producing a neuron output signal in response;

wherein said neuron input unit includes a selector connected to each of said plurality of input lines to select a weight-product corresponding to each of said plurality of input signals.

24. A neuron as in claim 23, wherein said neuron input unit further comprises an adder for adding each of said plurality of input signals, as modified by the weighting elements, together to form the intermediate signal.

25. A neuron for a neural processing network comprising:

a plurality of input lines for providing a plurality of input signals to said neuron;

a neuron input unit receiving said input signals and outputting an intermediate signal;

a delta sigma modulator receiving said intermediate signal from said neuron input unit and producing a neuron output signal in response;

wherein said delta sigma modulator includes a saturating adder receiving the intermediate signal from said neuron input unit and also receiving feedback through the neuron output signal.

26. An artificial neuron as in claim 25, wherein the saturating adder forms part of an integrator feedback loop.

27. An artificial neuron as in claim 26, wherein said delta sigma modulator includes a comparator connected to the output of said integrator, said comparator producing as an output the neuron output signal.

28. A neuron as in claim 25, wherein the saturating adder operates according to a sigmoidal function.

29. An artificial neuron receiving a plurality of input signals on a plurality of input signal lines, comprising:

a selector unit connected to each of said plurality of input lines, said selector unit selecting and applying a weighting element to each of said plurality of input signals to produce a weight-product on each of said input lines;

an adder for computing the sum of all weight-products and producing an intermediate output signal; and

a delta sigma modulator receiving said intermediate output signal and producing a neuron output signal.

30. An artificial neuron as in claim 29, wherein the selector unit comprises a multiplexer.

31. An artificial neuron as in claim 29, further comprising a second artificial neuron receiving the neuron output signal as an input signal.

32. An artificial neuron as in claim 29, wherein said delta sigma modulator includes an adder receiving said intermediate signal and said neuron output signal and producing an output signal in response.

33. An artificial neuron as in claim 29, further comprising a saturating adder and a latch, said saturating adder receiving as input signals the output from the delta sigma modulator adder and a feedback output from said latch, and producing in response an output signal that is produced as an input signal to said latch.

34. An artificial neuron as in claim 33, wherein said delta sigma modulator further comprises a comparator receiving the output from said latch and producing the neuron output signal.

35. An artificial neuron as in claim 34, wherein said comparator produces a high neuron output signal when the output of the latch is positive and a low neuron output signal when the output of the latch is negative.

36. An artificial neuron as in claim 29, further comprising a linear transfer function connected to the output of said adder.

37. An artificial neuron as in claim 29, wherein said adder comprises an adder tree.

38. An artificial neuron as in claim 37 wherein said adder comprises a plurality of two-input adders formed into layers.

39. An artificial neuron as in claim 38, wherein a latch is connected to the output of each two input adder.

40. An artificial neuron as in claim 37, wherein the delta sigma modulator is embedded in the adder tree.

41. An adaptive linear combiner, comprising:

a delta sigma modulator for inputting a signal and providing an output signal;

a shift register receiving the output signal from said delta sigma modulator and outputting a plurality of output signals;

a delta sigma neuron connected to the shift register for receiving the plurality of output signals and providing an output signal; and

a low pass filter and decimator connected to the delta sigma neuron and receiving the output signal from the delta sigma neuron.

42. A device as in claim 41, wherein said adaptive linear combiner operates as a finite impulse response filter.

43. A device as in claim 41, further comprising:

a second shift register supplying a plurality of input signals to said delta sigma neuron, with said second shift register receiving as an input signal the output signal from the delta sigma neuron.

44. A device as in claim 43, wherein said adaptive linear combiner comprises an infinite impulse response filter.