Stackable vertical thin package/plastic molded lead-on-chip memory cube

• US 5,543,660 A
• Filed: 09/22/1994
• Issued: 08/06/1996
• Est. Priority Date: 09/03/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dombroski, Edward J.
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/310,521
• Time in Patent Office: 684 Days
• Field of Search: 257/685, 257/686, 257/706, 257/707, 257/722, 257/666, 257/787
• US Class Current: 257/707
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49172 : by molding of insulating material

Abstract

This is a semiconductor chip package configuration particularly suited for stacking. These described arrangement is especially adapted to be used with the so-called Lead-On-Chip type package. Each package is of minimum size, and provided with a thermal heat sink arranged with respect to the remainder of the package to balance the stresses induced in the package during fabrication. This is accomplished by placing a lead frame on the active face of the semiconductor chip, bonding the lead frame conductors to respective input/output pads on the active face of the chip, and molding an encapsulant completely around five of the six sides of the chip but leaving a substantial portion of the sixth side unencapsulated. A heat sink is affixed on the exposed, i.e. unencapsulated, portion of the sixth side of the chip. The heat sink is comprised of a metal capable of thermally conducting and dissipating waste heat away from the chip and is of a mass, thickness, and area to counterbalance stresses such, as bending stresses, introduced into the chip by the application of the lead frame and encapsulant to the chip. The heat sink can also employed as a ground plane to provide an electromagnetic shield when the chips are arranged in a stack.

Claims

1. A semiconductor package comprising;

a semiconductor chip having a first major surface with input and output bonding pads thereon, a second major surface substantially parallel to said first major surface and four minor surfaces substantially perpendicular to said major surfaces and joining said major surfaces,

a lead frame having a plurality of conductors with distal and proximal ends, the proximal ends of the conductors being positioned adjacent said first major surface of said chip,

an insulating layer having a selected thickness positioned between and insulatively bonded to said proximal ends of said conductors and said first major surface,

an electrical connection between each respective one of said proximal ends of said conductors and a respective one of each of said bonding pads on the chip,

an insulating encapsulation disposed on and substantially enclosing said first major surface, said four minor surfaces, the proximal ends of said conductors and partially enclosing a portion of said distal ends of said conductors, a portion of said distal ends being cantilevered from said encapsulation, and

a metallic plate disposed on and in good thermal contact with said second major surface,

said plate having a thickness approximately equal to the sum of the thickness of said proximal ends of said lead frame and said insulating layer.

2. The package of claim 1 wherein said encapsulation extends in thickness past said second major surface to form a recess in said encapsulant around said second major surface, and said plate is disposed in said recess.

3. The package of claim 1 wherein

said distal ends of said conductors in said lead frame extend beyond said insulating layer and are cantilevered therefrom and the thickness of said plate is approximately equal to the thickness of said distal ends of said conductors.

4. The package of claim 1 wherein said proximal ends of said conductors is one half the thickness of said distal ends.

5. The package of claim 1 wherein said plate extends past one of said edges of said chip and is thermally coupled to said chip to conduct heat away from said chip.

6. The package of claim 4 wherein said plate has a thickness approximately equal to the thickness of the distal ends of said conductors.

7. The package of claim 1 wherein said encapsulation enclosing said first major surface is provided with a plurality of extending hemispheres.

8. The package of claim 7 wherein said encapsulation encloses at least a portion of second major surface, and is provided with a plurality of sockets that will mate with the extending hemispheres on the encapsulation enclosing the first major surface of any adjacent package.

9. The package of claim 5 wherein said encapsulation enclosing said first major surface is provided with a small recess to expose a selected portion of a selected one of said lead frame conductors.

10. The package of claim 1 wherein said encapsulation surrounding at least one of said surfaces is provided with a small recess to expose a selected portion of a selected one of said lead frame conductors.

11. The package of claim 10 wherein said encapsulation encloses at least a portion of said second major surface, said encapsulation on said second major surface including a small recess, and said plate is provided with an opening therein which aligns with said small recess on said second major surface, said opening being larger than said small recess.

12. The package of claim 10 wherein a capacitor resides in said recess and is coupled to said selected one of said lead frame conductors.

13. The package of claim 11 wherein a capacitor resides in said recess and is coupled to said selected one of said lead frame conductors.

14. A vertical thin package comprising:

an integrated circuit having an active side, a substantially planar back side, and four edges;

a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends;

a molded package encasing (1) said active side and said four edges of said chip, with said back side exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip;

a conductive plate thermally attached to said back side of said chip to conduct heat away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and

wherein said chip, said lead frame, said molded package and said metallic plate are designed and constructed so that said package has an overall thickness of no more than about 1.27 mm.

15. The package of claim 14 wherein said package includes;

an insulating layer having a selected thickness positioned between and insulatively bonded to said encapsulated portions of said lead frame and said active side,

said lead ends of said lead frame extending beyond said molded package and cantilevered therefrom.

16. A stack of semiconductor chip packages comprising;

a plurality of semiconductor chip packages, each chip package comprising;

a semiconductor chip having a first major surface with input and output bonding pads thereon, a second major surface substantially parallel to said first major surface and four minor surfaces substantially perpendicular to said major surfaces and joining said major surfaces,

a lead frame having a plurality of conductors with distal and proximal ends, the proximal ends of the conductors being positioned adjacent said first major surface of said chip,

an electrical connection between each respective one of said proximal ends of said conductors and a respective one of each of said bonding pads on the chip,

an insulating layer having a selected thickness positioned between and insulatively bonded to said proximal ends of said conductors and said first major surface,

an insulating encapsulation disposed on and substantially enclosing said first major surface, said four minor surfaces, the proximal ends of said conductors and partially enclosing a portion of said distal ends of said conductors, a portion of said distal ends being cantilevered from said encapsulation,

a metallic plate disposed on and in good thermal contact with said second major surface, and

said plate having a thickness substantially equal to the sum of the thickness of said proximal ends of said lead frame and the thickness of said insulating layer,

each semiconductor chip package, in said stack, having an adhesive layer disposed on the encapsulation disposed over any said first major surface positioned adjacent the metallic plate on an adjacent chip package.

17. The stack of claim 16 wherein each package is further provided with

said distal ends of said conductors in said lead frame extending beyond said insulating layer and cantilevered therefrom, and said proximal ends of said conductors is one half the thickness of said distal ends.

18. The stack of claim 16 wherein each plate affixed to a respective one of said packages extends out of said stack to conduct heat away from said stack.

19. The stack of claim 16 wherein each of said packages has in its encapsulation, on said first major side, a plurality of extending hemispheres and on said second major surface a plurality of sockets that will align with the extending hemispheres on the first major side on any adjacent package.

20. The stack of claim 16 wherein each of said packages is provided with a capacitor coupled to a selected one of said lead frame conductors in said package.

21. A stack of semiconductor chip packages comprising:

a plurality of semiconductor chip packages, each comprising;

an integrated circuit having an active side, a substantially planar back side, and four edges;

a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends;

a molded package encasing (1) said active side and said four edges of said chip, with said back side exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip;

a conductive plate attached to said back side of said chip in a manner permitting heat to be conducted away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and

said chip, said lead frame, said molded package and said metallic plate have an overall thickness of no more than about 1.27 mm.

22. The stack of claim 21 wherein each said package further includes;

an insulating layer having a selected thickness positioned between and insulatively bonded to said encapsulated portions of said lead frame and said active side, and said lead ends of said lead frame extend beyond said molded package and are cantilevered therefrom.

23. A stack of semiconductor chip packages comprising;

a plurality of substantially planar semiconductor packages having front surfaces and back surfaces,

the front surface of each of said chip packages being bonded to the back surface of any adjacent chip package in said stack by a layer a thermoplastic polyimide adhesive,

each of said chip packages comprising;

an integrated circuit having an active side, a substantially planar back side, and four edges;

a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends;

a molded package encasing (1) said active side and said four edges of said chip, with said back side of said chip exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip;

a conductive plate attached to said back side of said chip in a manner permitting heat to be conducted away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and

said thermoplastic adhesive has a bonding temperature of about 230 degrees Celsius.

24. The stack of claim 23 wherein said thermoplastic adhesive has a delamination temperature of 210 degree Celsius.