Control, reduction and equalization of delays in a driver stage

• US 5,543,739 A
• Filed: 03/31/1994
• Issued: 08/06/1996
• Est. Priority Date: 04/09/1993
• Status: Expired due to Term

• Current Assignee: Consorzio Per Il Sistema Informativo Csi Piemonte, SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: Consorzio Per Il Sistema Informativo Csi Piemonte, SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Milazzo, Patrizia, Bontempo, Gregorio, Alzati, Angelo
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LE, DINH THANH
• Application Number:
  US08/220,845
• Time in Patent Office: 859 Days
• Field of Search: 327/432, 327/379, 327/427, 327/377, 327/376, 327/375, 327/392, 327/393, 327/398, 327/374, 327/108, 327/170, 327/306, 327/387, 326/17, 326/20
• US Class Current: 327/108
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/163 Soft switching

Abstract

The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Claims

1. A control circuit, coupled to a driving node of a power transistor, for switching a load toward ground through said power transistor, comprising:

a first current generator, coupled to said driving node and controlled by a first switching signal producing a current for charging said driving node of the power transistor during a turn-on process;

a second current generator, controlled by a second switching signal which is complementary to said first switching signal, producing a current for discharging the driving node of the power transistor during a turn-off process; and

a third current generator, coupled to said driving node, controlled by a third switching signal, and producing an additional current for discharging said driving node only during a first phase of said turn-off process, until the power transistor has reached a near saturation condition;

a capacitance discharge current amplifier connected between the driving node of the power transistor and said ground and driven by the sum of said discharge current, produced by said second current generator controlled by said second switching signal, and of said additional current that is produced through an output branch of a current mirror, connected between the driving node of the power transistor and said ground and driven by said third current generator, which is controlled by a replica of said second switching signal; and

circuitry connected to said capacitance discharge current amplifier and said third current generator, for interrupting said additional driving current of said capacitance discharge current amplifier when the voltage on the driving node of the power transistor drops to a value close to that of saturation of the power transistor;

wherein said circuitry for interrupting said additional driving current comprises a diode-configured transistor connected to said output branch of said current mirror.

2. The control circuit of claim 1, wherein the power transistor and said diode-configured transistor are both DMOS transistors.

3. The control circuit of claim 1, further comprising a transistor operatively connected between said output branch of said current mirror and said ground and having a control terminal which is connected in common with the control terminals of a pair of transistors that form said current mirror, said transistor having a size as to turn-on when the voltage on the driving node of the power transistor drops to a preset value, thus diverting to the ground the output current of said current mirror.

4. An integrated control circuit, coupled to a driving node of a power transistor, for switching a load to ground, comprising;

a first current generator controlled by a first switching signal and connected for generating a charge current to turn on the power transistor by charging a driving node thereof by means of a charge current;

a current amplifying stage connected to turn off said power transistor by discharging the driving node thereof, at a rate which is dependent on a total control current received by said current amplifying stage;

a second current generator, controlled by a second switching signal, complementary to said first switching signal, and connected to supply a first control current component to said current amplifying stage;

a diode configured transistor connected to provide a second control current to said current amplifying stage; and

a third current generator, coupled to said drive node and said diode configured transistor controlled by said second switching signal, and operatively connected to supply a current proportional to said second control current to said diode configured transistor;

said diode configured transistor being operatively connected to sense the value of the voltage at said driving node of said power transistor and accordingly to impede the passage of said second control current toward said current amplifying stage when said power transistor is close to a saturation condition.

5. The integrated control circuit of claim 4, further comprising a current mirror connected between said diode configured transistor and said third current generator to provide said second control current to said diode configured transistor.

6. The integrated control circuit of claim 5, wherein said current mirror has a high current mirror ratio.

7. The integrated control circuit of claim 5;

further comprising a first transistor, coupled between said diode configured transistor and said ground, and having a control terminal which is connected in common with the control terminals of a pair of transistors that form said current mirror, to divert to said ground said current from said third current generator when the value of the voltage at said driving node of the power transistor reaches a predetermined value.

8. The integrated control circuit of claim 7, wherein said transistor has a width/length ratio such as to turn on after the power transistor exits from a triode operation condition and before the power transistor reaches a saturation condition.

9. The integrated control circuit of claim 4, wherein said current amplifying stage consists of a second transistor.

10. The integrated control circuit of claim 9, wherein said second transistor constituting said current amplifying stage is a bipolar transistor.

11. The integrated control circuit of claim 9, wherein said second transistor has a gain independent of process spread and temperature.

12. The integrated control circuit of claim 4, wherein said diode configured transistor has structural characteristics similar to that of the power transistor.

13. The integrated control circuit of claim 4, wherein said diode configured transistor and said power transistor are DMOS.

14. An integrated driver circuit, comprising;

a power transistor to drive the load;

a first current generator, coupled to a driving node of said power transistor, controlled by a first switching signal and connected to turn on said power transistor by charging said driving node thereof by a charge current;

a discharge transistor connected to said driving node to produce an amplified discharge current to turn off said power transistor by discharging the driving node thereof;

a second current generator controlled by a second switching signal, complementary to said first switching signal, connected to supply a first discharge current to a control node of said discharge transistor;

a diode configured transistor connected to said control node to provide a second discharge current;

a current mirror connected to provide said second discharge current to said diode configured transistor, said current mirror being connected to be powered from said driving node of said power transistor; and

a third current generator controlled by said second switching signal connected to said current mirror to supply a current proportional to said second discharge current to said current mirror;

said diode configured transistor being coupled between said current mirror and said control node to sense the value of the voltage at said driving node of said power transistor and accordingly to impede the passage of said second discharge current toward said discharge transistor when said power transistor is close to a saturation condition.

15. The integrated driver circuit of claim 14, wherein said current mirror has a high current mirror ratio.

16. The integrated driver circuit of claim 14, further comprising a first transistor, coupled between said diode configured transistor and ground, and having a control terminal which is connected in common with the control terminals of a pair of transistors that form said current mirror, to divert to ground said current from said third current generator when the value of the voltage at said driving node of the power transistor reaches a predetermined value.

17. The integrated driver circuit of claim 16, wherein said transistor has a width/length ratio such as to turn on after the power transistor exits from a triode operation condition and before the power transistor reaches a saturation condition.

18. The integrated driver circuit of claim 14, wherein said discharge transistor is a bipolar transistor.

19. The integrated driver circuit of claim 14, wherein said discharge transistor has a gain independent on process spread and temperature.

20. The integrated driver circuit of claim 14, wherein said diode configured transistor has structural characteristics similar to that of the power transistor.

21. The integrated driver circuit of claim 14, wherein said diode configured transistor and said power transistor are DMOS.

22. The integrated driver circuit of claim 14, wherein said power transistor is a power DMOS.

23. A method for reducing the turn-off delay time of a power transistor, a driving node of which is charged and discharged by means of first and second current generators, coupled to said driving node, controlled respectively by a first control signal, which is in phase opposition to a second control signal, to respectively charge and discharge the gate of the power transistor, comprising the steps of:

generating an additional discharge current by means of a third current generator which is controlled to turn on by a third control signal, which is in phase with said second control signal of said second current generator;

sensing the reaching by the voltage on said driving node of the power transistor of a value close to the saturation value; and

interrupting said additional discharge current before the power transistor enters saturation;

wherein said generating step uses at least one current mirror.

24. The method of claim 23, wherein said at least one current mirror is connected to pass said additional discharge current into a diode configured transistor, and said step of interrupting uses a transistor having a control terminal which is connected in common with the control terminals of a pair of transistors that form said current mirror, to divert current from said diode configured transistor.

25. A method for reducing the turn-off delay time of a power transistor, a driving node of which is charged and discharged by means of first and second current generators, coupled to said driving node, controlled respectively by a first control signal, which is in phase opposition to a second control signal, to respectively charge and discharge said driving node, comprising the steps of:

generating an additional discharge current by means of a third current generator which is controlled to turn on by a third control signal, which is in phase with said second control signal of said second current generator;

sensing the reaching by the voltage on said driving node of the power transistor of a value close to the saturation value; and

interrupting said additional discharge current before the power transistor enters saturation;

wherein said sensing step uses a diode configured transistor.

26. A method for reducing the turn-off delay time of a power transistor, a driving node of which is charged and discharged by means of first and second current generators, coupled to said driving node, controlled respectively by a first control signal which is in phase opposition to a second control signal, to respectively charge and discharge said driving node, comprising the steps of:

generating an additional discharge current by means of a third current generator which is controlled to turn on by a third control signal, which is in phase with said second control signal of said second current generator;

sensing the reaching by the voltage on said driving node of the power transistor of a value close to the saturation value; and

interrupting said additional discharge current before the power transistor eaters saturation;

wherein said power transistor is a DMOS transistor, and wherein said sensing step uses a diode configured DMOS transistor.

27. A method of controllable reducing the turn off delay time of a power transistor driving a load, comprising the steps of:

,

charging a driving node of the power transistor by means of a charge current generated according to a first switching signal;

discharging said driving node of the power transistor by means of first and second discharge currents generated according to a second switching signal, complementary to said first switching signal;

passing said second discharge current through a circuit stage sensing the voltage at said driving node of said power transistor; and

impeding the passage of said second discharge current toward said power transistor when the value of the voltage to said driving node of the power transistor is close to a voltage corresponding to saturation of said power transistor;

wherein said step of passing uses at least one current mirror.

28. The method of claim 27, wherein said at least one current mirror has a high current mirror ratio.

29. A method of controllably reducing the turn off delay time of a power transistor driving a load, comprising the steps of:

charging a driving node of the power transistor by means of a charge current generated according to a first switching signal;

discharging said driving node of the power transistor by means of first and second discharge currents generated according to a second switching signal, complementary to said first switching signal;

passing said second discharge current through a circuit stage sensing the voltage at said driving node of said power transistor; and

impeding the passage of said second discharge current toward said power transistor when the value of the voltage to said driving node of the power transistor is close to a voltage corresponding to saturation of said power transistor;

wherein said step of impeding uses a diode configured DMOS transistor.

30. The method of claim 29 wherein said power transistor is a DMOS transistor.