Apparatus for selecting frame buffers for display in a double buffered display system

• US 5,543,824 A
• Filed: 08/28/1995
• Issued: 08/06/1996
• Est. Priority Date: 06/17/1991
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Priem, Curtis, Moffat, Guy, Malachowsky, Chris, McIntyre, Bruce
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): Chow, Doon
• Application Number:
  US08/520,301
• Time in Patent Office: 344 Days
• Field of Search: 345/190, 345/185, 345/187, 345/189, 345/197, 345/201, 395/164, 395/165, 395/166, 395/121, 348/567
• US Class Current: 345/539
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of the first or the second frame buffers, apparatus for storing a signal indicating that the multiplexor is to select a different frame buffer to furnishing data to an output display, and apparatus for furnishing the stored signal to the multiplexor only at the completion of a frame on a display and before a new frame commences.

Claims

1. A double buffered output display system for displaying a plurality of frames of data, said double buffered output display system comprising:

a rendering engine for rendering said plurality of frames of data;

an output display for display of said plurality of frames of data;

a video timing generator, said video timing generator generating at least one timing signal, said timing signal having a vertical retrace period after complete scanning of a first display frame and before scanning of a next display frame, said video timing generator asserting an enabling signal during said vertical retrace period;

a first frame buffer, said first frame buffer coupled to receive a first frame of data from said rendering engine, said rendering engine writing said first frame of data when said output display is not displaying said first frame of data in said first frame buffer;

a second frame buffer, said second frame buffer coupled to receive a second frame of data from said rendering engine, said rendering engine writing said second frame of data when said output display is not displaying said second frame of data in said second frame buffer;

a multiplexor coupled to said first frame buffer and said second frame buffer for furnishing an output frame, said multiplexor furnishing said output frame by selecting from said first frame buffer or second frame buffer;

converter means coupled to said multiplexor and said output display, said converter means receiving said output frame from said multiplexor, said converter means converting said output frame from said multiplexor into a display signal for display on said output display;

input register means coupled to-said rendering engine for receiving and storing a frame completed signal from said rendering engine indicating that the multiplexor is to select a different frame buffer for generating said output frame; and

output register means coupled to said input register means and coupled to said video timing generator to receive said enabling signal, said output register means generating an output signal when said enabling signal from said video timing generator is asserted after said frame completed signal has been received from said input register means, said output signal coupled to said multiplexor and said rendering engine such that said output signal switches said multiplexor and said output signal informs said rendering engine when said multiplexor has been switched;

such that said multiplexor switches between said first frame buffer and said second frame buffer only during said vertical retrace period of said timing signal and informs said rendering engine when a switch occurs.

2. A double buffered output display system as claimed in claim 1 in which the rendering engine does not begin rendering after sending said frame completed signal to said input register means until said rendering engine receives the output signal from the output register means.

3. In a double buffered output display system comprising an output display, a first frame buffer, a second frame buffer, a rendering engine for writing data to said first frame buffer and second frame buffer, a multiplexor for furnishing data from either the first frame buffer or the second frame buffer to a converter means, said converter means converting said data into an analog display signal and passing said analog display signal to said output display, a register means for controlling said multiplexor, a video timing generator having a vertical retrace period after displaying a first display frame and before displaying a next display frame, a method for switching between said first frame buffer and said second frame buffer in said double buffered output display system, said method comprising the steps of:

converting a first frame of data received from said first frame buffer through said multiplexor into said analog display signal displayed onto said output display using said converter means;

rendering a second frame of data using said rendering engine into said second frame buffer during the converting of said first frame of data;

signaling said register means with a frame completed signal when said rendering engine has completed rendering said second frame of data, said rendering engine free to perform nonrendering processing;

switching said multiplexor when said timing signal enters a next vertical retrace period such that said converting means now converts data from said second frame buffer into said analog display signal displayed onto said output display; and

signaling said rendering engine when said multiplexor has switched from said first frame buffer to said second frame buffer such that rendering engine is informed that it may render into said first frame buffer;

such that said multiplexor only switches between said first frame buffer and said second frame buffer during a vertical retrace period.

4. The method for switching between said first frame buffer and said second frame buffer in said double buffered output display system as set forth in claim 3, wherein said rendering engine begins rendering in said second frame buffer only after being informed that said multiplexor has switched.