Horizontal contour emphasizing signal processor
First Claim
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1. A horizontal contour emphasizing signal processor in which an input luminance signal is converted to a first horizontal contour emphasizing signal, further comprising:
- detector means for detecting a period during which a change in the input luminance signal occurs,signal generator means for generating a generated signal during said period,multiplication means for multiplying said first horizontal contour emphasizing signal by said generated signal to produce a second horizontal contour emphasizing signal,delay means for delaying the input luminance signal for a predetermined period, andsynthesizinq means for adding said second horizontal contour emphasizing signal to the input luminance signal delayed by said delay means.
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Abstract
An improved horizontal contour emphasizing signal processor is provided with a detector to detect a period during which luminance signal changes are produced, a generator to generate a rectangular-wave signal during this period, and a multiplier for multiplying a first horizontal contour emphasizing signal derived from the luminance signal to the rectangular-wave signal to generate a second horizontal contour emphasizing signal, and in this case, a preshoot is added to the input luminance signal waveform at the starting part of a radical waveform change and an overshoot is added at the ending part of the waveform change in order to perform finer horizontal contour emphasizing.
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Citations
10 Claims
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1. A horizontal contour emphasizing signal processor in which an input luminance signal is converted to a first horizontal contour emphasizing signal, further comprising:
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detector means for detecting a period during which a change in the input luminance signal occurs, signal generator means for generating a generated signal during said period, multiplication means for multiplying said first horizontal contour emphasizing signal by said generated signal to produce a second horizontal contour emphasizing signal, delay means for delaying the input luminance signal for a predetermined period, and synthesizinq means for adding said second horizontal contour emphasizing signal to the input luminance signal delayed by said delay means.
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2. A horizontal contour emphasizing signal processor comprising;
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a first delay-circuit delaying an input luminance signal for an arbitrary period, a second delay-circuit delaying the output signal of the first delay-circuit for the arbitrary period, a first subtraction circuit subtracting the output-signal of said first delay-circuit from the input-signal of said first delay-circuit, a second subtraction circuit subtracting the output-signal of second delay-circuit from the input signal of said second delay-circuit, a first multiplication circuit multiplying the output-signal of the first subtraction circuit to the output-signal of the second subtraction circuit, a second multiplication circuit obtaining a power of the output-signal of said first multiplication circuit, a limiter limiting the amplitude of said power of the output-signal obtained by said second multiplication circuit, a third subtraction circuit subtracting the output-signal of said second subtraction circuit from the output-signal of said first subtraction circuit, a third multiplication circuit multiplying the output-signal of said third subtraction circuit to the output-signal of said limiter, and a synthesizing circuit combining the output-signal of said third multiplication circuit to the output-signal of said first delay-circuit. - View Dependent Claims (3)
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4. A horizontal contour emphasizing signal processor comprising;
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a first delay-circuit delaying an input luminance signal for an arbitrary period, a second delay-circuit delaying the output-signal of said first delay circuit for the arbitrary period, a first subtraction circuit subtracting the output-signal of said first delay-circuit from the input-signal of said first delay-circuit, a second subtraction circuit subtracting the output-signal of said second delay-circuit from the input-signal of said second delay-circuit, a third subtraction circuit subtracting the output-signal of said second subtraction circuit from the output-signal of said first subtraction circuit, a differential circuit differentiating the output-signal of said first delay-circuit, a first multiplication circuit obtaining a power of the output-signal of said differential circuit, a limiter limiting the amplitude of output signal of said first multiplication circuit, a second multiplication circuit multiplying the output of said third subtraction circuit to the output-signal of said limiter, and a synthesizing circuit synthesizing the output-signal of said second multiplication circuit with the output-signal of said first delay-circuit. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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Specification
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Current AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsKawakami, Shigeru, Miyata, Minoru
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Primary Examiner(s)Metjahic, Safet
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Assistant Examiner(s)HSIA, SHERRIE Y
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Application NumberUS08/418,247Time in Patent Office488 DaysField of Search348/625, 348/630, 348/629, 348/712, 348/26, 358/37, 358/166, 358/96, 358/162, 382/254, 382/266US Class Current348/625CPC Class CodesH04N 5/208 for compensating for attenu...
