Apparatus and method for sampling signals synchronous with analog to digital converter

• US 5,544,064 A
• Filed: 05/20/1994
• Issued: 08/06/1996
• Est. Priority Date: 05/20/1994
• Status: Expired due to Fees

• Current Assignee: Beckwith, Robert W.
• Original Assignee: Beckwith, Robert W.
• Inventors: Beckwith, Robert W.
• Primary Examiner(s): Trammell, James P.
• Application Number:
  US08/246,630
• Time in Patent Office: 809 Days
• Field of Search: 364/480-486, 364/494, 395/800, 324/77 R, 324/74, 324/78 D, 323/257, 307/31, 341/141, 361/35, 361/36, 361/76, 361/78-87
• US Class Current: 700/293
• CPC Class Codes: G01R 19/25 using digital measurement techniques

Abstract

This invention provides various methods and techniques for providing a synchronous programming of a microcontroller and its associated analog to digital converter for a maximum rate of taking digital samples of alternating current analog signals which techniques are selectively combined to provide microcontroller based controls and protective relays such as for use with electric utilities.

Claims

1. In an electronic device including an analog to digital converter (ADC) having result registers and a central processor unit (CPU), the method consisting of the steps of:

a) providing a CPU program consisting of steps and loops,

b) operating said ADC and CPU synchronously,

c) continuously producing digital samples of analog signals every "t" cycles,

d) storing said samples in said result registers,

e) updating at least one of said result registers with new digital samples every "r" clock cycles, and

f) reading said result registers integral multiples of "r'"'"'" clock cycles after said result registers are updated, wherein "r'"'"'" is not greater than "r",

g) providing an ADC controller having continuous scan control bits, result register control bits, and input channel select bits,

h) selecting analog signals by setting said input channel select bits,

i) setting said continuous scan control bits to obtain ADC conversions in a continuous round robin fashion,

j) directing digital samples to selected ones of said result registers by selection of said result register control bits, for sampling a selected analog signal on integral multiples of "t" clock cycles,

k) adding do-nothing operations as required to make the run time for each step and each loop of said CPU program an integral multiple of "t" clock cycles, and

l) obtaining samples of said selected analog signal by reading a selected result register during said steps and said loops

thereby maximizing the sampling rate of the selected analog signal and whereby said ADC and CPU programs operate synchronously to obtain digital samples of said analog signals.

2. A method as in claim 1 further including the steps of:

a) coupling analog signals which are AC signals to said ADC,

b) suppressing the negative half cycles of said AC signals,

c) processing digital samples of said AC signals as they are read in accordance with a synchronous measurement sub-program so as to make a partial computation of parameters of said AC signals, and

d) further processing said samples in accordance with a computation sub-program to obtain parameters for desired operation of said electronic device,

e) operating said synchronous measurement sub-program and said computation sub-program alternatively until said parameters indicate that said electronic device is required to provide control and protective outputs,

f) branching by said computation sub-program to an output sub-program when said requirement occurs, and

g) otherwise continuing said alternative operation.

3. A method as in claim 2 further including the steps of:

a) providing a microcontroller unit (MCU) having an asynchronous serial communications interface (SCI) including an address register,

b) reading the SCI address register only during each operation of said computations sub-program,

c) providing program branching in response to said reading, and

d) sending and receiving serial data in short bursts

wherein the portion of time taken by said device for communications is minimized.

4. A method as in claim 3 further including the steps of:

a) connecting said SCI of at least one said MCU to communicate with a computer functioning as a network interface module (NIM),

b) connecting said computer to a local area network (LAN),

c) providing common protocol requirements for said computer and said LAN,

d) programming said computer to providing man machine interfaces for said devices,

e) programming said computer to hand over the man machine functions for said devices to the LAN system when requested by said LAN system,

f) programming said computer to interrogate and obtain parameters and data from said devices, and

g) providing data and parameters obtainable from said devices to the LAN system when requested by said LAN system.

5. A method as in claim 2 further including the steps of:

a) providing an analog signal input representing an AC voltage E (signal E),

b) setting said result register control bits to perform consecutive conversions on the single channel specified by said input channel select bits,

c) providing a program step PS0, which is the exit statement of a previous synchronous measurement sub-program and the entrance statement for a subsequent computation sub-program and performing the following

d) switching said signal E into said ADC,

e) starting a program loop PL1,

f) reading samples of said registers in round robin fashion,

g) looking for a sample of signal E with the value of zero,

h) looking for a non-zero sample of signal E,

i) exiting to a subsequent program step PS1 after obtaining the first non-zero sample of signal E,

j) computing the square of the first sample of signal E and forming the sum of squares,

k) exiting to a subsequent program loop PL2,

l) taking samples of said registers in round robin fashion,

m) continuing summing the squares of the samples of signal E,

n) looking for a sample of signal E with the value zero and branching to said computation sub-program when zero is sensed,

o) using the results of the summation of squares in said computation sub-program to provide control parameters for said electronic devices, and

whereby control parameters are provided to operate electrical equipment responsive to the magnitude of voltage E.

6. A method as in claim 5 wherein steps j) and m) consist of using the sum of samples method in lieu of the sum of the square of samples method for computation.

7. A method as in claim 5 further including the steps of:

a) providing analog signals input representing AC currents,

b) reading said result registers every integral multiple of "t" cycles to provide digital samples of said current signals,

c) calculating sums of said integral multiples as each digital sample is taken, starting with the first zero to non-zero transition (znz) in the value of said digital samples of said signal E and ending with each succeeding znz and non-zero to zero (nzz) transition of said current signals,

d) switching signals representing currents, one at a time, into said ADC,

e) finding znz for each current signal,

f) reading ADC result registers,

g) forming the sum of squares of non-zero samples until a zero sample is read,

h) exiting to said computations sub program after the last current signal has been switched to the ADC, and

i) using said sums of integral multiples of said ADC conversion cycles "t" to compute the phase angle from voltage signal E to each current signal

whereby said sums of squares and phase angles are provided to obtain modification of said control parameters.

8. A method as in claim 7 wherein step g) consists of using the sum of samples method in lieu of the sum of the square of samples method for computation.

9. A method as in claim 2 further including the steps of:

a) having AC voltage input signals with phase rotation in the order EA'"'"', EB'"'"', EC'"'"' from three phases of an electric power circuit,

b) setting said result register control bits to perform consecutive conversions on the single channel specified by said input channel select bits,

c) taking digital samples from said ADC using program loops operating in an integral "n" multiple, together with program steps operating in an integral "m" multiple, of the number of clock cycles "t" required for an analog to digital conversion,

d) selecting said AC input signal EA'"'"',

e) finding a zero to non-zero (znz) transition in said digital samples,

f) starting a sum "N" of "n" and "m",

g) recording the first non-zero sample of said AC signal EA'"'"' as "a",

h) finding and recording a peak voltage factor EA for said signal EA'"'"',

i) finding a non-zero to zero (nzz) transition in said digital samples,

j) replacing said signal EA'"'"' with said signal EC'"'"',

k) finding and recording a peak voltage factor EC for said signal EC'"'"',

l) finding a nzz transition in said digital samples,

m) replacing said signal EC'"'"' with said signal EB'"'"',

n) finding and recording a peak voltage factor EB for said signal EB'"'"',

o) finding a nzz transition in said digital samples,

p) replacing said signal EB'"'"' with said signal EA'"'"',

q) finding the first znz transition in said digital signals,

r) recording the first non-zero signal as "a'"'"'",

s) recording the sum "N",

t) determining Emax as the largest of EA, EB, EC,

u) determining E/Hz in time units of one clock cycle from the relation;

space="preserve" listing-type="equation">E/Hz=Emax*(N-1)*t*(1*(a-a'"'"')/(4π

*EA))

v) selectively determining E/Hz in time units of seconds by multiplying by the length of one clock cycle in seconds

thereby obtaining E/Hz parameters for use in said electronic devices to provide outputs for controlling and protecting electrical apparatus.

10. A method as in claim 9 further including the steps of:

a) finding the geometric mean of the frequencies in the frequency range of said E/Hz device,

b) providing a first and a second set of scaling resisters from each of three said input voltage signal sources to provide six inputs to said ADC,

c) selecting ADC inputs provided by said first set of scaling resisters when a frequency below said geometric mean frequency is detected,

d) selecting ADC inputs provided by said second set of scaling resisters when a frequency above said geometric mean frequency is detected,

e) selecting said scaling resisters such that expected magnitudes of voltages will not saturate said ADC over the frequency range of said E/Hz device

whereby said E/Hz device will operate over a wide range of frequency.

11. A method as in claim 10 further including the step of determining the period P of said AC signal EA'"'"' in time units of one clock cycle using the equation:

space="preserve" listing-type="equation">P=(N-1)*t*(1+(a-a'"'"')/(2π

*EA))

thereby obtaining frequency parameters for use in selecting said scaling resisters.

12. A method as in claim 1 further including the steps of:

a) providing first and second AC signals of a first polarity respectively representing input and output currents of an electrical equipment,

b) providing third and fourth AC signals respectively representing said input and output currents with polarities reversed,

c) providing fifth and sixth AC signals respectively representing said input and output currents of first polarity,

d) providing seventh and eighth AC signals respectively representing said input and output currents with polarities reversed,

e) scaling said first, second, third, and fourth AC signals for linear ADC operation over a first range of current magnitudes,

f) scaling said fifth, sixth, seventh and eighth AC signals for linear ADC operation over a second range of current magnitudes,

g) arranging inputs into four pairs of signals comprising said first and second signals, said third and fourth signals, said fifth and sixth signals, and said seventh and eighth signals,

h) taking continuous periodic digital samples of said input signals, alternating between ascending order of said first to eighth signal numbers, and descending order of said first to eighth signal numbers,

i) comparing samples of each said pair when taken in ascending order with samples of each said pair when taken in descending order,

j) averaging at least the last two differences of each of said four pairs of samples, whereby errors developed by said ADC when said digital samples are taken in ascending order are averaged and compensated for by taking the samples in descending order,

k) using said average differences to obtain parameters for providing corrective outputs of said electronic device

such as for tripping a circuit breaker.

13. A method as in claim 12 further comprising the steps of:

a) providing said input current signals from auxiliary current transformers having center tapped secondaries,

b) each said auxiliary current transformer providing said signals of opposite polarity from each other,

c) providing a first pair of auxiliary transformers for said input current,

d) providing a second pair of auxiliary transformers for said output current,

e) the first of each of said pairs of transformers being linear over the range of expected current magnitudes,

f) the second of each of said pairs saturating above the current magnitude from normal load currents,

g) obtaining said first, second, third, and fourth said AC signals from said first auxiliary transformers of said pairs of transformers,

h) obtaining said fifth, sixth, seventh, and eighth said AC signals from said second auxiliary transformers of said pairs of transformers,

whereby the second of each pair of transformers provides linear operation of said electronic device above a level where the first transformer of the pair saturates.

14. In an electronic device including a central processor unit (CPU) operating at a constant clock frequency, the method comprising the steps of:

a) providing a program for said CPU consisting of program steps and program loops each operating in an integral multiple of a number of clock cycles, "t",

b) summing said integral for each said step and each turn of said loop starting said sum at a first selected time and ending said sum at a second selected time,

c) providing an analog to digital converter (ADC) for converting AC signals to digital samples, said ADC having an analog to digital conversion time equal to "t",

d) reading digital samples at a first AC signal from said ADC with said program steps and said program loops operating synchronously with analog to digital conversions of said ADC,

e) selecting a change in polarity of said first AC signal as said starting time,

f) selecting the same change in polarity of a later cycle of said first AC signal as the ending point

whereby said sum is a measure of the frequency of said AC signal.

15. A method as in claim 14 wherein step f) consists of:

a) selecting the same change in polarity of a cycle of a second AC signal having the same frequency as the said first AC signal as the ending point

whereby said sum becomes a measure of the phase angle from said first signal to said second signal.

16. A method as in claim 14 further consisting of the steps of:

a) providing an AC signal input to said ADC having the digital samples of the negative half cycles of said AC signal input suppressed to zero,

b) taking digital samples of said AC signal input from said ADC using program loops operating in an integral "n" multiple, together with program steps operating in an integral "m" multiple, of the number of clock cycles "t" required for an analog to digital conversion,

c) taking the first non-zero digital sample "a" following a sample whose value is zero of said AC signal as said starting point,

d) finding the peak value "EA" of said AC signal input,

e) taking a subsequent second non-zero digital sample "a'"'"'" following a sample whose value is zero of said AC signal input, "R" cycles later than the cycle when said sample "a" was taken, as said ending point,

f) forming a sum "N" of "n" and "m" from said starting point to said ending point,

g) determining the period P of said AC signal input for R cycles of said AC signal input in time units of one clock cycle using the equation;

space="preserve" listing-type="equation">P=(N-1)*t*(1+((a-a'"'"')/2π

*EA))

and

h) selectively determining the period P for one cycle of said AC signal input in time units of one clock cycle by dividing P by R

thereby obtaining frequency parameters for use in said electronic device.

17. Apparatus for digitizing alternating current (AC) signals, each AC signal coming from a first and second signal terminal with the potential of said first terminal being the ground reference for said signal and with the signal potential of said second terminal alternating about said reference potential comprising, in combination,

a) clocking means providing clock cycles,

b) analog-to-digital converter means (ADC) operable by said clocking means and having a conversion period equal to a predetermined number "t" of clock cycles, said ADC having at least one analog input, having a low and a high reference voltage input and having a range of operation starting with zero for an analog input equal to said low reference input voltage,

c) processor means also operable by said clocking means,

d) multiple result register means for storing digital samples converted by said ADC,

e) said processor means running said ADC in a continuously scanning mode with conversions of the data of any selected analog input in a round robin fashion for storing in said multiple result registers wherein digital samples of each said AC signal are updated in integral numbers of clock cycles,

f) means for connecting a high ADC reference voltage means to said high reference input,

g) each of said second signal terminal being connected to a selected ADC analog input resulting in signals on said second terminals having a selected polarity which is the same as the polarity of said ADC high voltage reference,

h) said ADC having said low reference input connected to a ground reference terminal to set the change of signal polarity to said ADC zero,

i) said processor means containing programming steps which selectively repeat with said programming steps operating in integral multiples "m" of said "t" clock cycles and said programming steps operating synchronously with said continuous scanning mode of said ADC,

j) said ADC providing periodic non-zero digital samples proportional to said AC signals whenever the polarity of said AC signal is the same as said high reference voltage and providing digital samples which are zero whenever said AC signals are not of the selected polarity, and

k) means for processing said non-zero digital samples to make measurements to obtain parameters of said AC signals.

18. Apparatus for controlling and protecting electric power apparatus in response to measurement of volts per hertz in alternating current (AC) signals, three said AC signals being of the same frequency and representing the three phases voltages of a three phase circuit, comprising, each signal coming from a pair of terminals with the potential of one terminal being the ground reference for said signal and with the signal potential of the second terminal alternating about said reference potential, said apparatus comprising in combination,

a) means for providing clock cycles,

b) a central processing unit (CPU) means operable by said clock cycles,

c) an analog-to-digital converter means (ADC) operable by said clock cycles and having a conversion period equal to a predetermined number "t" of clock cycles, said ADC having at least one analog input, having a low and a high reference voltage input and having a range of operation starting with zero for an analog input equal to said low reference input voltage,

d) means for connecting said three AC signals to said ADC means,

e) means for setting said ADC to perform consecutive conversions on said three signals,

f) means for connecting a high ADC reference voltage means to said high voltage reference input,

g) means for connecting said ADC low reference input to each said AC signal ground reference terminal to set the change of signal polarity to ADC zero,

h) said processor means operating said ADC in a continuously scanning mode to sequentially convert a selected one of said three AC signals into digital data and store said data in a round-robin fashion into multiple result registers,

i) said processor means containing programming means consisting of steps which selectively repeat and with said programming steps operating in integral "m" multiples of "t" clock cycles to thereby operate synchronously with the continuous scanning mode of said ADC,

j) said ADC means providing periodic non-zero digital samples proportional to said selected AC signals whenever the polarity of said selected AC signal is the same as said high reference voltage and providing digital samples which are zero whenever said AC signal is not of the selected polarity, and

i) said processor means receiving and processing said digital samples to selectively determine the maximum amplitude among the three phase voltages, to enable determination of said AC signal frequency and said volts per hertz from which desired control and protection output signals may be obtained.

19. Apparatus for measuring, controlling and protecting electric power equipment in response to measurement of frequency comprising, in combination,

a) means for digitizing at least one alternating current (AC) signal, each said signal coming from a first and second terminal with the potential of said first terminal being the ground reference for said signal and with the signal potential of said second terminal alternating about said reference potential,

b) a clocking means providing clocking cycles,

c) an analog-to-digital converter means (ADC) operable by said clocking means, having at least one analog input, having a low and a high voltage reference input and having a range of operation starting with zero for an analog input equal to said low reference input voltage,

d) a processor means operably responsive to said clocking means,

e) multiple result register means for storing conversions of said ADC,

f) said processor means operating said ADC in a continuously scanning mode with conversions of the data on any selected analog input in a round-robin fashion for storing in said multiple result registers wherein AC signals are updated on integral multiples of said conversion time of "t" clock cycles,

g) means for providing a high ADC reference voltage to said ADC high voltage reference input,

h) means for connecting at least one of said second AC signal terminal to a selected ADC analog input resulting in the signals on said associated second terminal having a selected polarity which is the same as the polarity of said ADC high reference voltage,

i) said ADC means having said low voltage reference input connected to each said AC signal ground terminal to set a change of signal polarity to said ADC zero,

j) said processor containing programming means consisting of steps which selectively repeat and with said programming steps operating in integral multiples of "t" clock cycles thereby forming a programming which operates synchronously with said continuous scanning mode of said ADC,

k) said ADC means providing periodic non-zero digital samples proportional to said AC signals whenever the polarity of said AC signal is the same as said high reference voltage and providing zeros whenever said AC signal is not of the selected polarity,

l) said processor means receiving and processing said digital samples to determine the approximate frequency from the time difference between changes from zero to non-zero samples at the start of two selected half cycles of said selected polarity,

m) means for determining the maximum amplitude of each said selected half cycle, and

n) means for processing the first non-zero sample of each said selected half cycle together with said maximum amplitudes of said selected half cycle to enhance the accuracy of the measurement of frequency of said AC signal.

20. Apparatus for digitizing alternating current (AC) signals comprising, in combination,

a) auxiliary transformer means with a center tapped secondary winding having a center tap terminal and with a first and a second terminal providing first and second signals of opposite polarity each of said first and second signals representing said AC signal and with the potential of said center tap terminal being the ground reference for said signal and with the signal potential of the first and the second terminal alternating about said reference potential,

b) said auxiliary current transformer means having a primary winding coupled to receive one AC signal,

c) analog-to-digital converter means (ADC) having at least one analog input representing said AC signal having a low and a high reference voltage input and having a range of operation starting with zero for an analog input equal to said low reference input voltage,

d) a high ADC reference voltage connected to said high reference input,

e) each said first and second terminals being connected to said ADC analog inputs resulting in signals on said first and second terminals having selected polarities which are the same as the polarity of said ADC high reference voltage,

f) said ADC having said low reference input connected to each said AC signal center tap terminal to set the change of signal polarities to said ADC zero,

g) said ADC providing periodic non-zero digital samples proportional to each said AC signal whenever the polarity of said AC signal is the same as said high reference voltage and providing zeros whenever said AC signal is not of the selected polarity, and

h) means for receiving and processing said digital samples to make a desired measurement of said signals using only samples proportional to the selected polarity

whereby each entire AC signal is digitized and zero crossings identified.

21. In an electronic device including an analog to digital converter (ADC) and a central processor unit (CPU) having a common clock, said ADC having result registers, ADC controller scan control bits, result register control bits, and analog channel select bits, the method comprising the steps of:

a) selecting analog signals by setting said analog channel select bits,

b) setting said scan control bits to obtain ADC conversions in a continuous round robin fashion,

c) taking digital samples from said ADC using program loops operating in an integral "n" multiple, together with program steps operating in an integral "m" multiple, of the number of clock cycles "t" required for an analog to digital conversion, and

d) summing said integral for each said step and each turn of said loop starting said sum at a first selected time and ending said sum at a second selected time

whereby said sum becomes a measure of the time interval from said starting time to said ending time.