Method of I/O pin assignment in a hierarchial packaging system

• US 5,544,088 A
• Filed: 06/19/1995
• Issued: 08/06/1996
• Est. Priority Date: 06/23/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Herasimtschuk, Michael, Checca, Ronald P., Granato, Michael A., Jurkovic, Michael J., Haeussler, David A., Zehr, Paul R., Broker, Harold J., Aubertine, Matthew E., Salem, Gerard M., Selinger, Craig R., Beyzavi, Kianoush
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/492,415
• Time in Patent Office: 414 Days
• Field of Search: 395/800, 395/309, 395/299, 395/730, 395/732, 395/185.09, 395/739, 395/54, 395/600, 365/222, 364/490, 364/488, 364/DIG. 2, 364/DIG. 1, 364/578, 364/580, 364/712, 364/489, 364/491, 340/825.5, 370/85.2
• US Class Current: 716/113
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level. I/Os assignment by this method for a computer system package design reduces the occurance of any critical nets failing length, electrical or timing constraints due to poor I/O assignments. The method has built in checks to avoid being trapped in an NP complete situation (a form of endless loop).

Claims

1. A method of assigning I/O pins for a physical circuit package system having multiple levels of packaging hierarchy, including a highest level and a lowest level wherein lower levels of packaging communicate with each other via higher levels of packaging, comprising the steps of:

(a) inputting net priorities into an iterative assignment process for making I/O pin assignments for connections between packages in the circuit package system, and starting at the highest level of packaging for the physical circuit package system, and moving progressively to lower levels until completed wherein successively lower levels each become the current level in sequence from the highest level to the lowest level, iteratively processing assignment of I/O pins for each level when such level becomes the current level until the I/O pins are stabilized, via steps of;

(b) propagating all I/O pin assignments to all higher level packaging of the physical circuit package system,

(c) running system timing with the I/O pin assignment and locations used during the preceding propagating step,

(d) determining if the run was performed at the lowest level, and if the run was performed at the lowest level, exiting from the method at the lowest level as stabilized I/O pin assignments for the physical circuit package, and if the run was not performed at the lowest level

(e) moving to a lower level in said sequence to make such lower level the current level, making the I/O pin assignments for the current level of packaging, and then

(f) checking the I/O pin assignments for any significant change between the I/O pin assignments after step (e), and the previous assignments for the current level of packaging immediately before step (e), and if there was no change, providing the I/O pin assignments for the current level to the testing step (d) of the process, and if there was a change providing the I/O pin assignments for the current level to the propagating step (b) of the process whereupon the I/O pin assignments are processed by step (b) and a succeeding step (c) of the process.

2. The method according to claim 1 wherein

the inputting step includes user established net priorities and estimated I/O locations and I/O weighting for assignment of locations.

3. The method according to claim 1 wherein the multiple levels include, from the highest level of the system of the circuit package, additional levels in descending order, including, in descending order a cable level, a board level, a module or card level, and a chip level for which the net priorities are established and I/O pin location assignments provided as a result of the process.

4. The method according to claim 1 wherein the step (b) propagates all assignments of pin locations to all of the higher package levels, and as the process is iterative, if there is an output at checking step (f) which shows that there is a needed change for I/O pin assignment, the output of checking step (f) becomes an input to propagating step (b), and during step (b), the program propagates the assignment an location of the higher package levels for the needed changes, resulting in an output of propagating step (b) which is an input to testing step (c).

5. The method according to claim 4 wherein the method begins with inputting a planned placement of all components at each system level and a logical association of all nets in accordance with top-down design.

6. The method according to claim 5 wherein in propagating step (b) estimated I/O locations are calculated based on direction in which net wire has to travel to make a connection at the current and next levels of packaging hierarchy.

7. The method according to claim 5 wherein in propagating step (b) net priorities, apart from net priorities determined by timing information, are established based on length or electrical constraint.

8. The method according to claim 5 wherein in propagating step (b) weighting based on physical characteristics of I/O pins which would affect performance are also established.

9. The method according to claim 5 wherein in propagating step (b) the I/O pin assignments and locations of the I/O pin assignments at the current level are propagated to each higher package level so that wire lengths and timing are re-calculated at the higher levels, and when step (b) is initially invoked in the method, placement and net priority information are used for the current level being the highest package level, and wherein subsequent invocations of step (b) cause component I/O locations at the current level to be propagated to the highest level.

10. The method according to claim 5 wherein in timing run step (c) system level timing is executed and slack values which represent the difference between a required arrival time and an actual arrival time are propagated to all package levels.

11. The method according to claim 5 wherein in timing run step (c) slack values are used to establish a net priority based on timing wherein nets having the smallest slack values have the highest priority for assignment.

12. The method according to claim 5 wherein net priorities are established independent of timing information and nets are given priority based on wire length constraints a necessity to minimize skew representing timing differences between a group of nets, or net type that indicates a critical or non-critical net.