Flash EEPROM system cell array with defect management including an error correction scheme

• US 5,544,118 A
• Filed: 03/07/1995
• Issued: 08/06/1996
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/400,034
• Time in Patent Office: 518 Days
• Field of Search: 365/182, 365/185, 365/218, 365/230.01, 365/230.03, 365/900, 365/185.09, 365/185.29, 365/185.31, 365/185.33, 365/200
• US Class Current: 365/218
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occured. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferably as part of the blocks themselves, in order to maintain an endurance history of cells within the block. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. In an integrated circuit memory system including an array of non-volatile floating gate memory cells wherein individual cells are addressable for programming and reading their states, a method of operating said memory system, comprising:

providing a plurality of distinct blocks of said memory cells, wherein the cells of the individual blocks are erasable together,

performing an erase operation upon the memory cells within at least one block,

after the erase operation is performed, determining whether there are any unerased cells within said at least one block and, if so, a number of such unerased cells,

comparing the number of unerased cells with a permitted number, said permitted number being substantially the maximum number of cells whose data, if bad, are correctable by an error correction scheme,

if the number of unerased cells within said at least one block is less than said permitted number, reprogramming memory cells within the erased at least one block with new data, and

if the number of unerased cells within said at least one block is greater than said permitted number, substituting other redundant memory cells for the unerased memory cells.

2. The method according to claim 1 wherein the substituting step includes determining address locations of the unerased cells within said at least one block, storing said address locations, and substituting redundant good cells therefor.

3. The method according to claim 1 which additionally comprises, if the number of unerased cells within said at least one block exceeds another number that is significantly larger than said permitted number, raising a flag.

4. The method according to claim 1 wherein the erase operation is performed as follows:

addressing said at least one block and initiating an erase cycle of the memory cells therein,

determining the states of the memory cells within said at least one block during the erase cycle, and

terminating the erase cycle either when all of the memory cells of said at least one block are determined to be erased or when a predefined condition is reached before all of the cells of said at least one block are erased.

5. The method according to claim 4 wherein said predefined condition includes reaching a condition where all of the memory cells within said at least one block have been erased except for said permitted number or less.

6. The method according to claim 1 which additionally comprises incrementing a running count of the number of times that said at least one block has been subjected to an erase cycle, and storing the incremented count.

7. The method according to claim 6, which additionally comprises, in response to said running count reaching a preset number, substituting a redundant block for said at least one block.

8. The method according to claim 6, wherein the incremented count is stored within said at least one block after the memory cells within said at least one block have been subjected to the erase cycle.

9. In an integrated circuit memory system including an array of non-volatile floating gate memory cells wherein individual cells are addressable for programming and reading their states, a method of operating said memory system, comprising:

providing a plurality of distinct blocks of said memory cells, wherein the cells of the individual blocks are erasable together to a base state from which one or more of the memory cells within an erased block may be subsequently reprogrammed,

addressing at least one of said plurality of blocks and initiating an erase cycle of the memory cells therein,

determining the states of the memory cells within said at least one block during the erase cycle,

terminating the erase cycle either when all of the memory cells of said at least one block are determined to be erased to the base state or when a predefined condition is reached before all of the cells of said at least one block are erased,

if the erase cycle is terminated before all the cells of said at least one block are erased, determining whether the number of unerased memory cells within said at least one block is less than or greater than a permitted number, said permitted number being substantially the maximum number of cells whose data, if bad, are correctable by an error correction scheme,

if the number of unerased cells within said at least one block is less than said permitted number, reprogramming memory cells within the erased said at least one block with new data, and

if the number of unerased cells within said at least one block is greater than said permitted number, substituting other redundant memory cells for the unerased memory cells.

10. The method according to claim 9 wherein the substituting step includes determining address locations of the unerased cells within said at least one block, storing said address locations, and substituting redundant good cells therefor.

11. The method according to claim 9 wherein said predefined condition of the erase cycle includes reaching a condition where all of the memory cells within said at least one block have been erased except for said permitted number or less of memory cells within said at least one block.

12. The method according to claim 9 wherein the erase cycle comprises application of a plurality of erase pulses to the memory cells within said at least one block with their states being determined in between the erase pulses.

13. The method according to claim 12 wherein said predefined condition of the erase cycle includes reaching a given number of erase pulses during the erase cycle.

14. The method according to claim 12 wherein the plurality of erase pulses are increased in magnitude during the erase cycle, and wherein said predefined condition includes when the magnitude of the erase pulses reach a predetermined maximum level.