Method for assuring that an erase process for a memory array has been properly completed

• US 5,544,119 A
• Filed: 09/06/1995
• Issued: 08/06/1996
• Est. Priority Date: 10/30/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven E., Magnusson, Eric J.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/522,980
• Time in Patent Office: 335 Days
• Field of Search: 365/900, 365/218, 365/189.01, 365/230.01, 365/182, 365/185, 365/185.29, 365/185.30, 365/185.33, 371/21.6, 371/10.1, 371/10.2
• US Class Current: 365/185.11
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.

Claims

1. A method for ensuring an erase operation has been reliably performed on a first block of a flash EEPROM memory array, the flash EEPROM memory array including a plurality of blocks, the method comprising the steps of:

a) writing a first data element to a second block when the erase operation on the first block is about to commence;

b) writing a second data element to the second block if the erase operation on the first block is successfully completed;

c) testing the second block to determine whether the first and second data elements have been written to the second block, if power is reapplied to the flash EEPROM memory array; and

d) subsequently reinitiating the erase operation on the first block if the first data element has been written to the second block and the second data element has not been written to the second block.

2. The method of claim 1, wherein the first data element is written to a data area of a sector in the second block and the second data element is written to a header area of the sector in the second block.

3. The method of claim 2, wherein the writing of the second data element in step (b) invalidates the sector in the second block.

4. The method of claim 1, wherein subsequent to the reinitiated erase operation of the first block in step (d), steps (b)-(d) are repeated.