Delay test coverage without additional dummy latches in a scan-based test design

• US 5,544,173 A
• Filed: 06/07/1995
• Issued: 08/06/1996
• Est. Priority Date: 08/18/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Meltzer, David
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/486,112
• Time in Patent Office: 426 Days
• Field of Search: 371/22.3, 371/22.1, 371/22.5, 371/27
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31858 Delay testing
• CPC Class Codes: G01R 31/318586 with partial scan or non-scannable parts

Abstract

Scan testing of complex electronic logic circuits for the detection of AC delay faults is improved without the addition of dummy or test-only latches by connecting the shift register latches according to the order determined by the method of first listing all shift register latches in the scan chain with all the combinational circuit outputs traceable from the output; sorting this list in the order of number of outputs controlled, i.e., touched in the forward trace; listing each unique combinational circuit output; sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs; when this is not possible assign adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, insert an output SRL between adjacent SRLs. The additional consideration of physical distance between SRLs may be added as an ordering criterion.

Claims

1. A method of configuring a digital integrated logic circuit having a plurality of interconnected combinational circuits, each having at least one input and at least one output, and a plurality of daisy chained flip-flops arranged as a scan chain of shift register latches, each shift register latch having an output and a scan input, and wherein the output of each of the shift register latches is connected to either an input of one of the plurality interconnected combinational elements or to a primary output of said digital integrated circuit, and is connected to the scan chain input of another shift register latch by a method comprising the steps of:

determining the order of connection of said shift register latches in said scan chain to maximize the number of circuits tested for AC delay faults; and

in the process assigning a scan chain order by;

a. creating a list of all shift register latches (SRLs) in the scan chain with all the combinational circuit outputs traceable from said primary output;

b. sorting said list in the order of number of circuit outputs controlled by being touched in a forward trace of said combinational circuits;

c. listing each unique combinational circuit output;

d. sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs.

2. The method in accordance with claim 1 and further comprising the following steps:

when successful assignment according to step d. is not possible, assigning adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, then sequentially inserting an output shift register latch between adjacent SRLs.

3. The method of claim 1 wherein weighted preference is given to assigning adjacent SRLs to the scan chain which are physically closest to each other on the integrated circuit chip.