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Delay test coverage without additional dummy latches in a scan-based test design

  • US 5,544,173 A
  • Filed: 06/07/1995
  • Issued: 08/06/1996
  • Est. Priority Date: 08/18/1994
  • Status: Expired due to Fees
First Claim
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1. A method of configuring a digital integrated logic circuit having a plurality of interconnected combinational circuits, each having at least one input and at least one output, and a plurality of daisy chained flip-flops arranged as a scan chain of shift register latches, each shift register latch having an output and a scan input, and wherein the output of each of the shift register latches is connected to either an input of one of the plurality interconnected combinational elements or to a primary output of said digital integrated circuit, and is connected to the scan chain input of another shift register latch by a method comprising the steps of:

  • determining the order of connection of said shift register latches in said scan chain to maximize the number of circuits tested for AC delay faults; and

    in the process assigning a scan chain order by;

    a. creating a list of all shift register latches (SRLs) in the scan chain with all the combinational circuit outputs traceable from said primary output;

    b. sorting said list in the order of number of circuit outputs controlled by being touched in a forward trace of said combinational circuits;

    c. listing each unique combinational circuit output;

    d. sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs.

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