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Cellular digtial packet data mobile data base station

  • US 5,544,222 A
  • Filed: 11/12/1993
  • Issued: 08/06/1996
  • Est. Priority Date: 11/12/1993
  • Status: Expired due to Term
First Claim
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1. A mobile data base station (MDBS) configured to transfer cellular digital packet data (CDPD) between at least one mobile subscriber and an external communication network (MD-IS), said MDBS comprising:

  • a controller board operatively connected to said MD-IS via a data link, arranged to receive and convey operating instructions and comprising(a) a flash EPROM containing a boot-up code to initiate data flow into said MDBS,(b) a first SRAM arranged to increase the capacity of the first control processor,(c) a DRAM arranged to store operational codes used by said first control processor, and(d) a hard disk drive arranged to store all control programming in said MDBS,all (a), (b), (c) and (d) operatively connected to said first control processor;

    a plurality of transceiver boards providing radio links to mobile subscribers, said transceiver boards each being separate and distinct from said controller board,wherein said MDBS is co-located with a cellular control and switching station configured as an Advanced mobile Phone System (AMPS) base station,wherein said controller board and said transceiver board are operatively interconnected through a backplane,wherein said controller board comprises a first control processor programmed for radio resource management and generation of control commands to said transceiver board and a first input/output (I/O) processor programmed for routing data throughout said MDBS, said first control processor and said first I/O processor being operatively connected to each other,wherein said first control processor is operatively connected to said data link through said first I/O processor, and said first I/O processor is also operatively connected to said backplane,wherein said first I/O processor is operatively connected to said backplane through a high level data link channel (HDLC), andwherein said controller board further comprises a dynamically programmable random access memory DRAM operatively connected to facilitated communication between said first control processor and said first I/O processor.

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