Flexible dram access in a frame buffer memory and system
First Claim
Patent Images
1. A frame buffer memory, comprising:
- memory array for buffering a set of pixel data that defines an image for display on a display device, the memory array arranged as a set of memory banks, each memory bank comprising a set of memory cells and a set of sense amplifiers coupled to access the memory cells;
pixel cache coupled to access the sense amplifiers of each memory bank, the pixel cache comprising a plurality of pixel cache blocks and a set of dirty tag bits corresponding to each pixel cache block;
pixel ALU coupled to the pixel cache and coupled to a rendering bus;
memory access circuit coupled to the memory array and to the pixel cache, the memory access circuit coupled to receive a memory access request that specifies a memory access function and one of the memory banks, the memory access circuit having circuitry for initiating the memory access function according to the memory access request;
pixel access circuit coupled to the pixel cache and coupled to receive a pixel access request that specifies one of the pixel cache blocks, the pixel access circuit having circuitry for initiating a pixel access over the rendering bus to the pixel cache according to the pixel access request.
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Abstract
A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
197 Citations
61 Claims
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1. A frame buffer memory, comprising:
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memory array for buffering a set of pixel data that defines an image for display on a display device, the memory array arranged as a set of memory banks, each memory bank comprising a set of memory cells and a set of sense amplifiers coupled to access the memory cells; pixel cache coupled to access the sense amplifiers of each memory bank, the pixel cache comprising a plurality of pixel cache blocks and a set of dirty tag bits corresponding to each pixel cache block; pixel ALU coupled to the pixel cache and coupled to a rendering bus; memory access circuit coupled to the memory array and to the pixel cache, the memory access circuit coupled to receive a memory access request that specifies a memory access function and one of the memory banks, the memory access circuit having circuitry for initiating the memory access function according to the memory access request; pixel access circuit coupled to the pixel cache and coupled to receive a pixel access request that specifies one of the pixel cache blocks, the pixel access circuit having circuitry for initiating a pixel access over the rendering bus to the pixel cache according to the pixel access request. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for accessing pixel data in a frame buffer random access memory device including, comprising the steps of:
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receiving a memory access request that specifies a memory access function and one of a set of memory banks of a memory array, each memory bank comprising a set of memory cells for buffering a set of pixel data that defines an image for display on a display device; receiving a pixel access request that specifies one of a plurality of pixel cache blocks in a pixel cache; performing the memory access function according to the memory access request while performing a pixel access to the pixel cache according to the pixel access request. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A computer system, comprising:
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processor coupled to transfer a set of graphics data over a system bus, the graphics data corresponding to an image for display on a display device; rendering controller coupled to receive the graphics data over the system bus, the rendering controller coupled to transfer a memory access request, a pixel access request, and a pixel value over a rendering bus; frame buffer memory device comprising a memory array arranged as a set of memory banks, and a pixel cache comprising a plurality of pixel cache blocks, the frame buffer memory device coupled to receive the memory access request that specifies one of the memory banks, and coupled to receive the pixel access request that specifies one of the pixel cache blocks, the frame buffer memory device having circuitry for performing a memory access function according to the memory access request, and circuitry for performing a pixel access over the rendering bus to the pixel cache according to the pixel access request. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. A frame buffer memory device, comprising:
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dynamic random access memory (DRAM) array comprising a plurality of DRAM cells for buffering a set of pixel data that defines an image for display on a display device; sense amplifiers coupled to the DRAM cells of the DRAM array circuitry for transferring the pixel data from a first page of the DRAM array to the sense amplifiers according to an access page command received over a rendering bus; circuitry for transferring the pixel data from the sense amplifiers to a second page of the DRAM array according to a duplicate page command received over the rendering bus. - View Dependent Claims (54, 55, 56)
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57. A method for performing block fill operations in a frame buffer, comprising the steps of:
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receiving an access page command over a rendering bus, the access page command specifying a first page of a dynamic random access memory (DRAM) array; transferring a set of pixel data from the first page of the DRAM array to a set of sense amplifiers; receiving duplicate page command over the rendering bus, the duplicate page command specifying a second page of the DRAM array; transferring the pixel data from the sense amplifiers to the second page of the DRAM array. - View Dependent Claims (58, 59, 60, 61)
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Specification