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Method and system for controlling cache memory with a storage buffer to increase throughput of a write operation to the cache memory

  • US 5,544,340 A
  • Filed: 12/22/1994
  • Issued: 08/06/1996
  • Est. Priority Date: 06/01/1990
  • Status: Expired due to Fees
First Claim
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1. A cache memory control method for controlling a cache memory disposed between a central processing unit (CPU) and a main memory, said cache memory being subdivided into a plurality of banks, said method comprising the steps of:

  • storing in a first-in/first-out (FIFO) buffer included in said CPU a plurality of pairs of data and addresses, each of said pairs including data and an address to be written into respective data and address banks of said plurality of banks in said cache memory;

    comparing respective address fields of said plurality of pairs of data and an address read from said buffer memory;

    generating, based on results of said comparing step, a write control signal for writing said data in said cache memory; and

    simultaneously writing said plurality of pairs of data and an address each into respective ones of said plurality of banks of said cache memory using the write control signal determined by said generating step, said addresses of said pairs being different from each other.

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