Method and system for controlling cache memory with a storage buffer to increase throughput of a write operation to the cache memory

• US 5,544,340 A
• Filed: 12/22/1994
• Issued: 08/06/1996
• Est. Priority Date: 06/01/1990
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ishibashi, Kenichi, Doi, Toshio, Takemoto, Takeshi, Hayashi, Takehisa
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Peikari, James
• Application Number:
  US08/362,755
• Time in Patent Office: 593 Days
• Field of Search: 395/400, 395/425, 395/875, 395/824, 395/872, 395/445, 395/456, 395/459, 364/DIG. 1
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0886 Variable-length word access

Abstract

A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

Claims

1. A cache memory control method for controlling a cache memory disposed between a central processing unit (CPU) and a main memory, said cache memory being subdivided into a plurality of banks, said method comprising the steps of:

storing in a first-in/first-out (FIFO) buffer included in said CPU a plurality of pairs of data and addresses, each of said pairs including data and an address to be written into respective data and address banks of said plurality of banks in said cache memory;

comparing respective address fields of said plurality of pairs of data and an address read from said buffer memory;

generating, based on results of said comparing step, a write control signal for writing said data in said cache memory; and

simultaneously writing said plurality of pairs of data and an address each into respective ones of said plurality of banks of said cache memory using the write control signal determined by said generating step, said addresses of said pairs being different from each other.

2. A cache memory control method according to claim 1, wherein

each of said plurality of banks of said cache memory is supplied with independent addresses, data, and write control signals, and

the number of bits constituting said independent data within each of said plurality of banks of said cache memory equals the number of bits contained in a data field of each of said pairs of data and an address held in said buffer memory.

3. A cache memory control method according to claim 1, wherein

said CPU is configured in a one-chip LSI which includes said buffer memory, and

said cache memory includes an SRAM chip connected to said LSI.

4. A cache memory control method according to claim 3, wherein

said data field of each of said pairs of data and an address stored in said buffer memory is 64 bits long,

said buffer memory reads out two pairs of data and an address at the same time, said cache memory is subdivided into two banks;

a data field of each of said banks is 64 bits long, and

each of said two banks has a data line connected to pins of said LSI, with a one-to-one correspondence established between said data lines and said pins.

5. A cache memory control method according to claim 4, wherein the operation to keep data to be written in said buffer memory in a 128-bit cache memory necessitates handling of two pairs of data and an address.

6. A cache memory control method according to claim 3, wherein

said LSI includes therein a first layer cache memory, and

a second layer memory includes an SRAM.

7. A cache memory control method for controlling a cache memory provided between a central processing unit (CPU) and a main memory, said cache memory being subdivided into a plurality of banks, said method comprising the steps of:

storing a plurality of pairs of data and an address, each of said pairs including data and an address to be written into respective data and address banks of said cache memory, in a first-in/first-out (FIFO) buffer included in said CPU;

providing a register including therein an address of said cache memory, said address being previously used for a write operation;

comparing an address field of said pair of data and an address read from said buffer memory with said register content; and

generating, based on a result of said comparing step, a write control signal for writing said data in one of said plurality of banks of said cache memory.

8. A cache memory control method according to claim 7, wherein

said CPU comprises a one-chip LSI including said memory, and

said cache memory includes an SRAM chip connected to said LSI.

9. A computer including a cache memory disposed between a central processing unit (CPU) and a main memory, said cache memory being subdivided into a plurality of banks, comprising:

a first-in/first-out (FIFO) buffer included in said CPU having a plurality of entries therein for holding a plurality of pairs of data and an address, each of said pairs including data and one of said addresses to be written from said CPU into respective banks of said cache memory;

means for processing said plurality of pairs of data and addresses from said buffer memory for comparing respective address fields of said plurality of pairs of data and addresses;

means for generating, based on results of said comparisons, a write control signal for writing said data in said cache memory, said cache memory being subdivided into a plurality of banks; and

means for simultaneously writing said plurality of pairs of data and addresses each into respective ones of said plurality of banks of said cache memory using the write control signal determined by said determining means, said addresses being different from each other.

10. A computer having a cache memory disposed between a central processing unit (CPU) and a main memory, said cache memory being subdivided into a plurality of banks, comprising:

a first-in/first-out (FIFO) buffer included in said CPU having a plurality of entries therein for holding data and addresses to be written into respective banks of said cache memory, said data and said addresses being paired with each other;

a register for holding therein an address of said cache memory, said address being previously used for a write operation therein;

means for comparing an address field of one of said pairs of data and an address read from said buffer memory with said register;

means for generating, based on a result of the comparison, a write control signal for writing said data into said cache memory.