Method for fabricating self-assembling microstructures

• US 5,545,291 A
• Filed: 12/17/1993
• Issued: 08/13/1996
• Est. Priority Date: 12/17/1993
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Smith, John S., Yeh, Hsi-Jen J.
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/169,298
• Time in Patent Office: 970 Days
• Field of Search: 156/626, 156/627, 156/633, 156/649, 156/655, 156/657, 156/662, 156/631, 437/8, 437/180, 437/086, 437/209, 437/225, 437/226, 29/592
• US Class Current: 438/107
• CPC Class Codes: G02F 1/136 Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit G02F1/135 takes precedence
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/83136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/95092 Atmospheric pressure, e.g. dry self-assembly
• CPC Class Codes: H01L 2224/95122 by applying vibration
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/04 : the devices not having separate containers
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15155 : the shape of the recess being other than a cuboid
• CPC Class Codes: H01L 2924/15157 : Top view
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 33/20 : with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01S 5/02251 : using optical fibres
• CPC Class Codes: H01S 5/02326 : Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
• CPC Class Codes: H01S 5/183 : having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

Abstract

A method for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate 20, 70, 90, 120, 200. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then poured evenly over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Claims

1. A method of assembling a microstructure on a substrate, said substrate comprising a top surface with at least one recessed region thereon, comprising the steps of:

providing a plurality of shaped blocks, said shaped block comprising an integrated circuit device thereon;

transferring said shaped blocks into a fluid to form a slurry; and

dispensing said slurry over said substrate at a rate where at least one of said shaped blocks is disposed into a recessed region.

2. The method of claim 1 wherein said substrate is selected from a group consisting of a silicon wafer, plastic sheet, gallium arsenide wafer, glass substrate, and ceramic substrate.

3. The method of claim 1 wherein said rate is substantially a laminar flow and allows each of said shaped blocks to self-align into said recessed region.

4. The method of claim 1 Wherein said shaped blocks include a trapezoidal profile.

5. The method of claim 4 wherein each of said recessed regions in said substrate is shaped substantially trapezoidal to complement each of said shaped blocks.

6. The method of claim 4 wherein said trapezoidal shaped blocks include a length at about 10 μ

m and greater.

7. The method of claim 1 wherein said fluid is an inert fluid selected from a group consisting of water, acetone, and alcohol.

8. The method of claim 1 wherein said slurry includes enough fluid to allow said shaped blocks to slide across said substrate.

9. The method of claim 4 wherein said trapezoidal blocks are fabricated by a method comprising the steps of:

providing a second substrate having a top surface;

growing a sacrificial layer overlying said top surface;

forming a block layer overlying said top surface;

masking and etching said block layer up to said sacrificial layer forming a plurality of trapezoidal shaped blocks on and in contact with said sacrificial layer;

preferential etching said sacrificial layer lifting off each of said trapezoidal shaped blocks; and

transferring said trapezoidal shaped blocks into a solution to form said slurry.

10. The method of claim 9 further comprising a step of rinsing said blocks subsequent to said preferential etching step.

11. The method of claim 9 wherein said preferential etching step is a step of wet etching.

12. The method of claim 9 wherein said wet etching step includes a hydrogen fluoride etchant.

13. The method of claim 9 wherein said second substrate is selected from the group consisting of gallium arsenide, gallium aluminum arsenide, silicon, and diamond.

14. The method of claim 4 wherein said trapezoidal shaped block further comprising a truncated pyramid shape including a top surface with four sides protruding therefrom to a base.

15. The method of claim 14 wherein said base has a length between about 10 μ

m and about 50 μ

m, and a width between 10 μ

m and about 50 μ

m, and each of said four sides has a height between about 5 μ

m and about 15 μ

m.

16. A method of fabricating shaped blocks comprising an integrated circuit device, comprising the steps of:

providing a substrate having a top surface and a backside;

growing a sacrificial layer made from a material selected from the group consisting of aluminum arsenide, indium phosphate and silicon dioxide overlying said top surface;

forming a block layer overlying said top surface; and

masking and etching said block layer up to said sacrificial layer forming a plurality of shaped blocks on and in contact with said sacrificial layer.

17. The method of claim 16 further comprising a step of preferential etching said sacrificial layer lifting off each of said shaped blocks.

18. A method of fabricating shaped blocks comprising an integrated circuit device, comprising the steps of:

providing a substrate having a top surface and a backside;

growing a sacrificial layer overlying said top surface;

forming a block layer overlying said top surface; and

masking and etching said block layer up to said sacrificial layer forming a plurality of shaped blocks on and in contact with said sacrificial layer;

depositing a filler layer onto a top surface of said shaped blocks and exposed portions of said sacrificial layer;

attaching a top surface of an intermediate substrate onto said top surface of said shaped blocks;

removing said substrate from said shaped blocks;

processing portions of said shaped blocks, said processing step forming integrated circuit devices on said blocks; and

removing said filler layer and said shaped blocks from said intermediate substrate.

19. A method of fabricating shaped blocks comprising an integrated circuit device, comprising:

providing a substrate including a release layer overlying the substrate, and a block layer overlying the release layer;

patterning said block layer to form a plurality of shaped blocks;

preferential etching said release layer to release said plurality of shaped blocks.

20. The method of claim 19 wherein said release layer is made from a material selected from the group consisting of aluminum arsenide, indium phosphate, and silicon dioxide.

21. The method of claim 19 wherein said patterning step includes reactive ion etching.

22. The method of claim 19 wherein said patterning step includes potassium hydroxide etching.

23. The method of claim 19 wherein said preferential etching step comprises hydrofluoric acid etching.

24. The method of claim 19 wherein each of said plurality of shaped blocks includes a sloped sidewall.

25. The method of claim 24 wherein said sloped sidewall is negative.

26. The method of claim 24 wherein said sloped sidewall is positive.