Method of maufacturing a semiconductor device having a low resistance gate electrode

• US 5,545,578 A
• Filed: 05/15/1995
• Issued: 08/13/1996
• Est. Priority Date: 06/08/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Yong-hee, Park, Young-hoon, Seo, Young-woo
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/440,954
• Time in Patent Office: 456 Days
• Field of Search: 437/44, 437/36, 437/913, 437/29, 437/983, 437/241, 148/DIG. 117, 148/DIG. 147
• US Class Current: 438/303
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for manufacturing a semiconductor device, e.g., an LDD transistor, which includes the steps of forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the gate insulating layer, forming a silicide layer on the polysilicon layer, etching the silicide layer to form a gate-patterned silicide layer, and over-etching the silicide layer to partially etch the polysilicon layer, to thereby form a step in the polysilicon layer, forming an oxidation-prevention spacer on sidewalls of the gate-patterned silicide layer and sidewalls of the polysilicon layer exposed by the step, etching the polysilicon layer, using the oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, the gate-patterned silicide layer and the gate-patterned polysilicon layer together comprising a gate electrode, thermally oxidizing exposed portions of the gate insulating layer and exposed portions of the polysilicon layer, to thereby form an oxide layer, and, ion-implanting impurities into the semiconductor substrate, using the resultant structure as an ion-implantation mask, to thereby form source/drain regions in the semiconductor substrate, on opposite sides of the gate electrode.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate insulating layer on a semiconductor substrate;

forming a polysilicon layer on said gate insulating layer;

forming a silicide layer on said polysilicon layer;

etching said silicide layer to form a gate-patterned silicide layer, and over-etching said silicide layer to partially etch said polysilicon layer, to thereby form a step in said polysilicon layer;

forming an oxidation-prevention spacer on sidewalls of said gate-patterned silicide layer and sidewalls of said polysilicon layer exposed by said step;

etching said polysilicon layer, using said oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, said gate-patterned silicide layer and said gate-patterned polysilicon layer together comprising a gate electrode;

thermally oxidizing exposed portions of said gate insulating layer and exposed portions of said polysilicon layer, to thereby form an oxide layer; and

,

ion-implanting first impurities into said semiconductor substrate, using the resultant structure from the previously-recited steps as an ion-implantation mask, to thereby form source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

2. The method as set forth in claim 1, further comprising the steps of:

forming a further spacer on sidewalls of said oxidation-prevention spacer; and

,

ion-implanting second impurities into said semiconductor substrate, to a greater depth than said first impurities, using said further spacer as an ion-implantation mask, to thereby form deeper source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

3. The method as set forth in claim 2, wherein said first impurities are n^- impurities, and said second impurities are n⁺ impurities.

4. The method as set forth in claim 1, wherein said silicide layer comprises a refractory silicide layer.

5. The method as set forth in claim 4, wherein said refractory silicide layer comprises a tungsten silicide layer.

6. The method as set forth in claims 1 or 4, wherein said oxidation-prevention spacer is comprised of a nitride material.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate insulating layer on a semiconductor substrate;

forming a polysilicon layer on said gate insulating layer;

forming a silicide layer on said polysilicon layer;

forming an oxidation-prevention layer on said silicide layer;

etching said oxidation-prevention layer and silicide layer to form a gate-patterned oxidation prevention layer and a gate-patterned silicide layer, and over-etching said silicide layer to partially etch said polysilicon layer, to thereby form a step in said polysilicon layer;

forming an oxidation-prevention spacer on sidewalls of said gate-patterned oxidation-prevention layer, sidewalls of said gate-patterned silicide layer, and sidewalls of said polysilicon layer exposed by said step;

etching said polysilicon layer, using said oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, said gate-patterned silicide layer and said gate-patterned polysilicon layer together comprising a gate electrode;

thermally oxidizing exposed portions of said gate insulating layer and exposed portions of said polysilicon layer, to thereby form an oxide layer; and

,

ion-implanting first impurities into said semiconductor substrate, using the resultant structure from the previously-recited steps as an ion-implantation mask, to thereby form source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

8. The method as set forth in claim 7, further comprising the steps of:

forming a further spacer on sidewalls of said oxidation-prevention spacer; and

,

ion-implanting second impurities into said semiconductor substrate, to a greater depth than said first impurities, using said further spacer as an ion-implantation mask, to thereby form deeper source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

9. The method as set forth in claim 8, wherein said first impurities are n^- impurities, and said second impurities are n⁺ impurities.

10. The method as set forth in claim 7, wherein said silicide layer comprises a refractory silicide layer.

11. The method as set forth in claim 10, wherein said refractory silicide layer comprises a tungsten silicide layer.

12. The method as set forth in claims 7 or 10, wherein said oxidation-prevention spacer is comprised of a nitride material.

13. The method as set forth in claims 7 or 10, wherein said oxidation-prevention layer is comprised of a nitride material.

14. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate insulating layer on a semiconductor substrate;

forming a polysilicon layer on said gate insulating layer;

forming a silicide layer on said polysilicon layer;

forming an insulating layer on said silicide layer;

etching said insulating layer and silicide layer to form a gate-patterned insulating layer and a gate-patterned silicide layer, and over-etching said silicide layer to partially etch said polysilicon layer, to thereby form a step in said polysilicon layer;

forming an oxidation-prevention spacer on sidewalls of said gate-patterned insulating layer, sidewalls of said gate-patterned silicide layer, and sidewalls of said polysilicon layer exposed by said step;

etching said polysilicon layer, using said oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, said gate-patterned silicide layer and said gate-patterned polysilicon layer together comprising a gate electrode;

thermally oxidizing exposed portions of said gate insulating layer and exposed portions of said polysilicon layer, to thereby form an oxide layer; and

,

ion-implanting first impurities into said semiconductor substrate, using the resultant structure from the previously-recited steps as an ion-implantation mask, to thereby form source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

15. The method as set forth in claim 14, further comprising the steps of:

forming a further spacer on sidewalls of said oxidation-prevention spacer; and

,

ion-implanting second impurities into said semiconductor substrate, to a greater depth than said first impurities, using said further spacer as an ion-implantation mask, to thereby form deeper source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

16. The method as set forth in claim 15, wherein said first impurities are n^- impurities, and said second impurities are n⁺ impurities.

17. The method as set forth in claim 14, wherein said silicide layer comprises a refractory silicide layer.

18. The method as set forth in claim 17, wherein said refractory silicide layer comprises a tungsten silicide layer.

19. The method as set forth in claims 14 or 17, wherein said oxidation-prevention spacer is comprised of a nitride material.

20. The method as set forth in claims 14 or 17, wherein said insulating layer is comprised of an oxide material.

21. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate insulating layer on a semiconductor substrate;

forming a polysilicon layer on said gate insulating layer;

forming a silicide layer on said polysilicon layer;

forming an oxidation-prevention layer on said silicide layer;

forming an insulating layer on said oxidation-prevention layer;

etching said insulating layer, said oxidation-prevention layer and silicide layer to form a gate-patterned insulating layer, a gate-patterned oxidation prevention layer and a gate-patterned silicide layer, and over-etching said silicide layer to partially etch said polysilicon layer, to thereby form a step in said polysilicon layer;

forming an oxidation-prevention spacer on sidewalls of said gate-patterned insulating layer, sidewalls of said gate-patterned oxidation-prevention layer, sidewalls of said gate-patterned silicide layer, and sidewalls of said polysilicon layer exposed by said step;

etching said polysilicon layer, using said oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, said gate-patterned silicide layer and said gate-patterned polysilicon layer together comprising a gate electrode;

thermally oxidizing exposed portions of said gate insulating layer and exposed portions of said polysilicon layer, to thereby form an oxide layer; and

,

ion-implanting first impurities into said semiconductor substrate, using the resultant structure from the previously-recited steps as an ion-implantation mask, to thereby form source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode,

22. The method as set forth in claim 21, further comprising the steps of:

forming a further spacer on sidewalls of said oxidation-prevention spacer; and

,

ion-implanting second impurities into said semiconductor substrate, to a greater depth than said first impurities, using said further spacer as an ion-implantation mask, to thereby form deeper source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode,

23. The method as set forth in claim 22, wherein said first impurities are n^- impurities, and said second impurities are n⁺ impurities.

24. The method as set forth in claim 21, wherein said silicide layer comprises a refractory silicide layer.

25. The method as set forth in claim 24, wherein said refractory silicide layer comprises a tungsten silicide layer.

26. The method as set forth in claims 21 or 23, wherein said oxidation-prevention spacer is comprised of a nitride material.

27. The method as set forth in claims 21 or 23, wherein said insulating layer is comprised of an oxide material, and said oxidation-prevention layer is comprised of a nitride material.

28. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate insulating layer on a semiconductor substrate;

forming a polysilicon layer on said gate insulating layer;

forming a silicide layer on said polysilicon layer;

forming an insulating layer on said silicide layer;

etching said insulating layer and said silicide layer, to form a gate-patterned insulating layer;

undercut-etching said silicide layer to form a gate-patterned silicide layer having a lesser width than that of said gate-patterned insulating layer, and over-etching said silicide layer to partially etch said polysilicon layer, to thereby form a step in said polysilicon layer;

forming an oxidation-prevention spacer on sidewalls of said gate-patterned insulating layer, sidewalls of said gate-patterned silicide layer, and sidewalls of said polysilicon layer exposed by said step;

etching said polysilicon layer, using said oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, said gate-patterned silicide layer and said gate-patterned polysilicon layer together comprising a gate electrode;

thermally oxidizing exposed portions of said gate insulating layer and exposed portions of said polysilicon layer, to thereby form an oxide layer; and

,

ion-implanting first impurities into said semiconductor substrate, using the resultant structure from the previously-recited steps as an ion-implantation mask, to thereby form source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

29. The method as set forth in claim 28, further comprising the steps of:

forming a further spacer on sidewalls of said oxidation-prevention spacer; and

,

ion-implanting second impurities into said semiconductor substrate, to a greater depth than said first impurities, using said further spacer as an ion-implantation mask, to thereby form deeper source/drain regions in said semiconductor substrate, on opposite sides of said gate electrode.

30. The method as set forth in claim 29, wherein said first impurities are n^- impurities, and said second impurities are n⁺ impurities.

31. The method as set forth in claim 28, wherein said silicide layer comprises a refractory silicide layer.

32. The method as set forth in claim 31, wherein said refractory silicide layer comprises a tungsten silicide layer.

33. The method as set forth in claims 28 or 30, wherein said oxidation-prevention spacer is comprised of a nitride material.