×

Solid state radiation detection panel having tiled photosensitive detectors arranged to minimize edge effects between tiles

  • US 5,545,899 A
  • Filed: 03/27/1995
  • Issued: 08/13/1996
  • Est. Priority Date: 12/06/1993
  • Status: Expired due to Term
First Claim
Patent Images

1. A solid state radiation detection panel adapted to receive radiation on a first surface, comprising:

  • a common substrate;

    a plurality of modules, each of said plurality of modules formed on a silicon wafer comprising;

    an array of photosensitive detectors arranged in a plurality of rows and a plurality of columns, each of said photosensitive detectors having a radiation sensitive area and producing an output; and

    circuit means distributed within each of said plurality of modules for selective addressing one of said photosensitive detectors by addressing one of said plurality of rows and one of said plurality of columns and reading said output of said one of said array of photosensitive detectors;

    each of said plurality of modules being arranged in a three dimensional structure in which said array of photosensitive detectors are arranged on a first surface of each of said plurality of modules covering substantially the entire area of said first surface, in which said circuit means is located within said module in an area away from said first surface opposite from said received radiation and wherein said plurality of modules of said solid state radiation detection panel are positioned immediately adjacent each other resulting in a near contiguous radiation sensitive area over the entire surface of said solid state radiation detection panel receiving said radiation;

    panel addressing means for selectively addressing one of said photosensitive detectors in each of said plurality of modules by addressing said circuit means within each of said plurality of modules;

    panel reading means for selectively reading the output of said one of said array of photosensitive detectors in each of said modules; and

    interconnection means positioned between said plurality of modules and said common substrate for connecting said circuit means of each of said plurality of modules to said panel addressing means and to said panel reading means, respectively.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×