Vertical type insulated-gate semiconductor device

• US 5,545,908 A
• Filed: 01/27/1994
• Issued: 08/13/1996
• Est. Priority Date: 12/09/1991
• Status: Expired due to Term

• Current Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Original Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Inventors: Tokura, Norihiro, Okabe, Naoto
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/098,396
• Time in Patent Office: 929 Days
• Field of Search: 257/139, 257/341, 257/342
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

Arsenic is diffused previously on a most outside surface of a n^- -type epitaxial layer (2), and after forming gate oxide films (3) and gate electrodes (4), p-type base regions (8) and n⁺ -type source layers (7) are formed in a self-aligned manner with the gate electrodes (4) by a DSA technique and double diffusion. Thereby, a lateral directional junction depth of the p-type base regions (8) is compensated at the most outside surface, and a channel length of channels (9) is shortened substantially. When designing a threshold voltage, an impurity density of the p-type base regions (8) can be set higher than that of the conventional device by an amount corresponding to an impurity density of the arsenic of the most outside surface, and p-type pinch layers (14) formed underneath the n⁺ -type source layers (7) of the p-type base regions are (8) are lowered correspondingly in resistance.

Claims

1. A vertical type insulated-gate semiconductor device comprising:

a semiconductor substrate having a first impurity concentration;

a semiconductor layer of a first conductivity type and having a second impurity concentration lower than said first impurity concentration of said semiconductor substrate, said semiconductor layer being located on said semiconductor substrate;

an insulated gate structure located on a main surface of said semiconductor layer, said insulated gate structure including a gate electrode;

a well region of a second conductivity type having a first vertical diffusion depth;

a source region of said first conductivity type formed within said well region, said well region and said source region being double-diffused laterally from an edge of said gate electrode into said main surface of said semiconductor layer below said gate electrode to thereby align a channel in a vicinity of said edge of said gate electrode, said channel being located at a surface of said well region below said gate electrode;

a diffusion layer of said first conductivity type formed at said main surface of said semiconductor layer so as to overlap said channel, said diffusion layer having a third impurity concentration higher than said second impurity concentration of said semiconductor layer and a second vertical diffusion depth shallower than said first vertical diffusion depth of said well region, a net amount of a first impurity density of said first conductivity type of said diffusion layer being higher than a net amount of a second impurity density of said second conductivity type of said surface of said well region where said channel is formed;

a compensated region of said first conductivity type formed below said gate electrode and at said main surface of said semiconductor layer proximate to said well region, said compensated region eroding a configuration of said well region at said main surface of said semiconductor layer and below said gate electrode; and

a length of said channel being determined by a distance between said source region and said compensated region.

2. A vertical type insulated gate semiconductor device according to claim 1, wherein a net carrier density of said surface of said well region is compensated with said first impurity density of said first conductivity type of said diffusion layer and has a third impurity density of said second conductivity type lower than a fourth impurity density of said well region at a vertical depth deeper than said second vertical diffusion depth of said diffusion layer.

3. A vertical type insulated gate semiconductor device according to claim 2, wherein said second vertical diffusion depth of said diffusion layer is shallower than a junction depth of said source region.

4. A vertical type insulated gate semiconductor device according to claim 3, wherein said second vertical diffusion depth of said diffusion layer is approximately 0.5 μ

m and said junction depth of said source region is 0.7 μ

m.

5. A vertical type insulated gate semiconductor device according to claim 2, wherein said semiconductor substrate is of said first conductivity type.

6. A vertical type insulated gate semiconductor device according to claim 2, wherein said semiconductor substrate is of said second conductivity type.

7. A vertical type insulated gate semiconductor device according to claim 1, wherein said second vertical diffusion depth of said diffusion layer is shallower than a junction depth of said source region.

8. A vertical type insulated gate semiconductor device according to claim 7, wherein said second vertical diffusion depth of said diffusion layer is approximately 0.5 μ

m and said junction depth of said source region is 0.7 μ

m.

9. A vertical type insulated gate semiconductor device according to claim 7, wherein said semiconductor substrate is of said first conductivity type.

10. A vertical type insulated gate semiconductor device according to claim 7, wherein said semiconductor substrate is of said-second conductivity type.

11. A vertical type insulated gate semiconductor device according to claim 7, wherein first conductivity type impurities forming said diffusion layer have a diffusion coefficient smaller than that of second conductivity type impurities forming said well region.

12. A vertical type insulated gate semiconductor device according to claim 11, wherein said first conductivity type impurities are arsenic.

13. A vertical type insulated gate semiconductor device according to claim 1, wherein said semiconductor substrate is of said first conductivity type.

14. A vertical type insulated gate semiconductor device according to claim 1, wherein said semiconductor substrate is of said second conductivity type.

15. A vertical type insulated gate semiconductor device according to claim 1, wherein first conductivity type impurities forming said diffusion layer have a diffusion coefficient smaller than that of second conductivity type impurities forming said well region.

16. A vertical type insulated gate semiconductor device according to claim 15, wherein said first conductivity type impurities are arsenic.

17. A vertical type insulated gate semiconductor device comprising:

a semiconductor substrate having a first impurity concentration;

a semiconductor layer of a first conductivity type and having a second impurity concentration lower than said first impurity concentration of said semiconductor substrate, said semiconductor layer being located on said semiconductor substrate;

a diffusion layer of said first conductivity type formed at a main surface of said semiconductor layer and having a third impurity concentration higher than said second impurity concentration of said semiconductor layer;

an insulated gate structure located on said main surface of said semiconductor layer, said insulated gate structure including a gate electrode;

a well region of a second conductivity type having a vertical junction depth deeper than a vertical diffusion depth of said diffusion layer, a lateral diffusion length of said well region from an edge of said gate electrode into said main surface of said semiconductor layer below said gate electrode being shorter at a shallow portion than that at a deep portion, and a net first conductivity type impurity density at said diffusion layer being higher than a net second conductivity type impurity density at a surface of said well region where a channel is located;

a source region of said first conductivity type formed within said well region, said well region and said source region being double-diffused laterally from an edge of said gate electrode into said main surface of said semiconductor layer below said gate electrode to thereby align said channel in a vicinity of said edge of said gate electrode, said channel being located at said surface of said well region below said gate electrode; and

a compensated area of said first conductivity type disposed below said gate electrode and at said main surface of said semiconductor layer proximate to said well region.

18. A vertical type insulated gate semiconductor device according to claim 17, wherein said vertical diffusion depth of said diffusion layer is shallower than a junction depth of said source region.

19. A vertical type insulated gate semiconductor device according to claim 18, wherein said vertical diffusion depth of said diffusion layer is approximately 0.5 μ

m and said junction depth of said source region is 0.7 μ

m.

20. A vertical type insulated gate semiconductor device according to claim 18, wherein said semiconductor substrate is of said first conductivity type.

21. A vertical type insulated gate semiconductor device according to claim 18, wherein said semiconductor substrate is of said second conductivity type.

22. A vertical type insulated gate semiconductor device according to claim 18, wherein said impurities forming said diffusion layer have a first diffusion coefficient smaller than a second diffusion coefficient of said impurities forming said well region.

23. A vertical type insulated gate semiconductor device according to claim 22, wherein said impurities forming said diffusion layer are arsenic.

24. A vertical type semiconductor device comprising:

a semiconductor substrate;

a semiconductor layer of an N-type located on said semiconductor substrate;

a gate electrode located on a main surface of said semiconductor layer with a gate insulation film interposed therebetween;

at least two well regions, each of a P-type, formed at said main surface of said semiconductor layer, said at least two well regions being aligned with ends of said gate electrode;

an accumulation region of said N-type being disposed between said at least two well regions below said gate electrode;

at least two source regions of said N-type formed within said at least two well regions, respectively, a channel being defined in each of said at least two well regions at respective surfaces of said at least two well regions between a corresponding one of said at least two source regions and said accumulation region; and

a surface diffusion layer diffused at said main surface of said semiconductor layer including at least an area below said gate electrode, said surface diffusion layer having a first net donor density higher than a second net donor density of said semiconductor layer, and said surface diffusion layer having a diffusion depth shallower than a junction depth of said at least two well regions, whereby a net acceptor density below said gate electrode is compensated with said first net donor density of said surface diffusion layer and is lower at said channels than at said accumulation region;

wherein a width of said accumulation region is wider at a portion proximate to said channels than at a portion deeper than said surface diffusion layer.

25. A vertical type insulated gate semiconductor device according to claim 24, wherein said diffusion depth of said surface diffusion layer is shallower than a junction depth of said source region.

26. A vertical type insulated gate semiconductor device according to claim 25, wherein said diffusion depth of said surface diffusion layer is approximately 0.5 μ

m and said junction depth of said source region is 0.7 μ

m.

27. A vertical type insulated gate semiconductor device according to claim 25, wherein said semiconductor substrate is of said N-type.

28. A vertical type insulated gate semiconductor device according to claim 25, wherein said semiconductor substrate is of said P-type.

29. A vertical type insulated gate semiconductor device according to claim 25, wherein N-type impurities forming said surface diffusion layer have a first diffusion coefficient smaller than a second diffusion coefficient of P-type impurities forming said well region.

30. A vertical type insulated gate semiconductor device according to claim 29, wherein said N-type impurities forming said diffusion layer are arsenic.