Data output buffer with latch up prevention

• US 5,546,020 A
• Filed: 04/18/1995
• Issued: 08/13/1996
• Est. Priority Date: 04/18/1994
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Lee, Dong M., Hong, Hyeong S.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/423,860
• Time in Patent Office: 483 Days
• Field of Search: 326/83, 326/121, 327/534
• US Class Current: 326/83
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A data output buffer comprising a pull-up transistor having an N type-well, the pull-up transistor transferring a supply voltage from a supply voltage source to an output line in response to a logic state of data from an input line, a first PMOS transistor for switching the supply voltage from the supply voltage source to the N type-well of the pull-up transistor in response to a voltage on the output line, and a second PMOS transistor for feeding the voltage on the output line back to the N type-well of the pull-up transistor when the voltage on the output line is higher than the supply voltage from the supply voltage source. According to the present invention, the voltage on the output line can be prevented from being latched up to the supply voltage source when it is higher than the supply voltage from the supply voltage source. Therefore, the data output buffer has an enhanced operation speed and a minimized occupying area in a semiconductor integrated circuit device.

Claims

1. A data output buffer, comprising:

a pull-up transistor having an N-type well and transferring a supply voltage from a supply voltage source to an output line in response to a logic state of data from an input line;

switching means for switching the supply voltage from the supply voltage source to the N-type well of the pull-up transistor in response to a voltage on the output line; and

feedback means for feeding the voltage on the output line back to the N-type well of the pull-up transistor when the voltage on the output line is higher than the supply voltage from the supply voltage source;

wherein the feedback means includes a PMOS transistor having a gate connected to the supply voltage source, a drain connected to the N-type well of the pull-up transistor, and a source connected to the output line; and

the PMOS transistor has a threshold voltage lower than a voltage for turning on a junction between a drain and the N-type well of the pull-up transistor.