Charge dissipation in capacitively loaded ports

• US 5,546,039 A
• Filed: 04/17/1995
• Issued: 08/13/1996
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hewitt, Larry D., Feemster, Ryan
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/423,059
• Time in Patent Office: 484 Days
• Field of Search: 327/392-396, 327/399-401, 327/108-112, 327/379-391, 327/134, 327/170, 327/306, 327/309, 327/310, 327/313, 327/312, 327/551, 327/374-377, 326/21-25, 326/17, 326/82, 326/83, 326/87, 377/73-76, 377/56
• US Class Current: 327/379
• CPC Class Codes: G06F 3/16 Sound input; Sound output speech processing G10L
• CPC Class Codes: G06F 7/026 Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G10H 1/0066 using a MIDI interface
• CPC Class Codes: G10H 1/125 using a digital filter
• CPC Class Codes: G10H 2220/315 for joystick-like proportional control of musical input; Videogame input devices used for musical input or control, e.g. gamepad, joysticks joysticks per se G06F3/033, G05G9/047, A63F13/20
• CPC Class Codes: G10H 2230/035 Power management, i.e. specific power supply solutions for electrophonic musical instruments, e.g. auto power shut-off, energy saving designs, power conditioning, connector design, avoiding inconvenient wiring
• CPC Class Codes: G10H 2240/311 MIDI transmission G10H2240/056 takes precedence
• CPC Class Codes: G10H 2250/191 Chebyshev polynomials, e.g. to provide filter coefficients for sharp rolloff filters Chebyshev filters G10H2250/091; Chebyshev windows G10H2250/271
• CPC Class Codes: G10H 2250/545 Aliasing, i.e. preventing, eliminating or deliberately using aliasing noise, distortions or artifacts in sampled or synthesised waveforms, e.g. by band limiting, oversampling or undersampling, respectively
• CPC Class Codes: G10H 2250/571 Waveform compression, adapted for music synthesisers, sound banks or wavetables audio compression G10L19/00
• CPC Class Codes: G10H 2250/605 Dynamic range companding algorithms, e.g. "mu"-law, primarily used in the digital telephone systems of North America and Japan, or A-law as used in European digital telephone systems
• CPC Class Codes: G10H 2250/611 Waveform decimation, i.e. integer division of the sampling rate for reducing the number of samples in a discrete-time signal, e.g. by low-pass anti-alias filtering followed by the actual downsampling
• CPC Class Codes: G10H 7/002 using a common processing for different operations or calculations, and a set of microinstructions (programme) to control the sequence thereof
• CPC Class Codes: G10H 7/02 in which amplitudes at successive sample points of a tone waveform are stored in one or more memories
• CPC Class Codes: H03K 23/68 with a base which is a non-integer

Abstract

A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.

Claims

1. A method for regulating dissipation of electrical charge from capacitive loads on a port in a monolithic integrated circuit, said method comprising the steps of:

providing a chargeable capacitive load;

providing a load signal indicating the potential of said capacitive load;

linking said load signal to the integrated circuit ground through plural parallel gated transistors;

providing plural clock responsive triggering networks arranged in a sequential cascade, each selected one of said triggering networks having an output signal for controlling a corresponding selected one of said plural parallel gated transistors and an input signal clockable to appear as said output signal;

generating a digitally selected threshold signal;

comparing said load signal and said threshold signal to derive a pull-down signal;

supplying said pull-down signal as input signal of a leading triggering network of said sequential cascade;

clocking said plural triggering networks with a clocking signal to sequentially propagate the state of said pull-down signal forward through said leading triggering network and each subsequent one of said plural triggering networks to sequentially enable said plural paths in substantial timed correspondence with sequential state changes of said clocking signal.

2. The method of claim 1 wherein said plural triggering networks have an output-signal-determining input signal and further comprising the steps of:

supplying a system signal; and

disabling said plural parallel gated transistors in substantial coincidence by supplying said system signal as said output signal determining input signal of each selected one of said plural triggering networks.

3. The method of claim 1 wherein said sequential cascade is characterized by the arrangement of first and second ones of said plural triggering networks wherein said output signal of said first network provides said input signal of said second network and said input signal of said first network is clocked through said first network to appear as said output signal of said first network on a first state change of said clocking signal and said input signal of said second network is clocked through said second network to appear as said output signal of said second network on a second state change of said clocking signal.

4. The method of claim 1 wherein said sequential cascade is characterized by the linear arrangement of a first one and a second one of said plural triggering networks wherein the output signal of said first one of said plural triggering networks provides a signal state for the input signal of said second one of said plural triggering networks.

5. The method of claim 4 wherein said cascade responds to said clocking signal by propagating a determined state of said input signal of said first network to appear as the state of said output signal of said first network in correspondence with a state change of said clocking signal.

6. The method of claim 5 wherein said cascade responds to a further state change of said clocking signal by propagating said determined state of said output signal of said first network to appear as the state of said output signal of said second network.

7. The method of claim 2 wherein said capacitive load is charged through a variable resistance element in response to said disabling of said plural parallel gated transistors.

8. The method of claim 2 wherein one or more of said gated transistors comprise a dissipation transistor in series with a resistive element.

9. The method of claim 2 wherein said plural triggering networks are D flip-flops.

28. The method of claim 2 wherein said capacitive load is discharged in approximately 2 microseconds.

10. A method for reducing peak transition currents on a capacitively loaded port in a monolithic integrated circuit having an analog-to-digital and digital-to-analog signal conversion module and a digital audio signal synthesizer module, said method comprising the steps of:

providing a capacitively derived load signal;

linking said load signal to the integrated circuit ground through plural parallel paths, each path having a gated transistor and a resistor;

providing plural triggering networks arranged in a sequential cascade;

generating a digitally selected threshold signal;

comparing said load signal and said threshold signal to derive a pull-down signal;

supplying said pull-down signal as an input signal to said cascade;

clocking said plural triggering networks with a common clocking signal; and

sequentially enabling said plural parallel paths by supplying selected ones of said gated transistors with an output signal from selected corresponding ones of said plural triggering networks, said output signals derived sequentially as the state of said cascade input signal sequentially propagates through said cascade in substantial timed correspondence with said clocking signal.

11. The method of claim 10 wherein each of said plural triggering networks has an output-determinative input signal and further comprising the step of:

supplying a system signal; and

disabling said plural parallel paths in substantial coincidence by supplying said system signal as the output-determinative input signal of each of said plural triggering networks.

12. The method of claim 11 wherein said resistors of said plural parallel paths are scaled in value to limit maximum current during port transition to ground state from a value corresponding to said threshold signal.

13. The method of claim 11 wherein said load signal is generated by a system comprising a capacitor charged through a potentiometer.

14. The method of claim 13 wherein said system is a game joystick.

15. A method for regulating peak transition currents on a capacitively loaded port, said method comprising the steps of:

providing a monolithic integrated circuit;

providing said monolithic integrated circuit with a capacitively derived load signal;

linking said load signal to the integrated circuit ground through plural parallel paths, each path having a switchable transistor;

providing plural triggering networks arranged in a sequential cascade, said sequential cascade having an input signal;

supplying a pull-down signal as said cascade input signal;

propagating said pull-down signal through said cascade by sequentially activating said plural triggering networks; and

sequentially enabling said plural parallel paths by supplying selected ones of said switchable transistors with an output signal from selected corresponding ones of said sequentially activated plural triggering networks.

16. The method of claim 15 wherein a predetermined delay is interposed between said sequential activation of a first one of said plural triggering networks and a second one of said plural triggering networks.

17. The method of claim 16 wherein said monolithic circuit includes an analog-to-digital and digital-to-analog signal conversion module and a digital audio signal synthesizer module.

18. A method for regulating peak currents during a HIGH to LOW transition on a capacitively loaded port in a monolithic integrated circuit having an analog-to-digital and digital-to-analog signal conversion module and a digital audio signal synthesizer module, said method comprising the steps of:

providing a load signal;

linking said load signal to the integrated circuit ground through first, second, third, and fourth parallel paths, each path characterized by a gated transistor;

providing first, second, third, and fourth triggering networks, each selected one of said triggering networks having an output signal and an input signal clockable to appear as said output signal of said selected triggering network, said triggering networks arranged in a sequential cascade characterized by said output signal of said first triggering network providing said input signal for said second triggering network and said output signal of said second triggering network providing said input signal for said third triggering network and said output signal of said third triggering network providing said input signal for said fourth triggering network;

generating a digitally selected threshold signal;

comparing said load signal and said threshold signal to derive a pull-down signal;

supplying said pull-down signal as said input signal of said first triggering network of said sequential cascade;

clocking said first, second, third, and fourth triggering networks with a common clocking signal; and

sequentially enabling said first, second, third, and fourth parallel paths by supplying said gated transistors of said first, second, third, and fourth parallel paths with the corresponding said output signals from said first, second, third, and fourth triggering networks respectively, said output signals derived as said input signal of said first triggering network sequentially propagates through said cascade in substantial correspondence with sequential state changes of said common clocking signal.

19. The method of claim 18 wherein said load signal is generated by a game controller capacitor.

20. A system for regulating peak transition currents on a capacitively loaded port in a monolithic integrated circuit having an analog-to-digital and digital-to-analog signal conversion module and a digital audio signal synthesizer module, said system comprising:

an input port for receiving a capacitive load signal;

plural pull-down parallel paths linking said input port and the integrated circuit ground, each path characterized by a gated transistor;

a digital-to-analog convertor generating a selectable threshold signal;

a comparator generating a pull-down signal derived from the comparison of said load signal and said selectable threshold signal;

plural clock responsive triggering networks arranged in a sequential cascade, each selected one of said triggering networks having an output signal supplied to a selected corresponding one of said plural pull-down paths and an input signal clockable to appear as said output signal of said selected triggering network; and

a clocking circuit having a clock-derived signal supplied in substantial coincidence to each of said plural triggering networks to sequentially propagate the state of said pull-down signal through said cascade to sequentially activate said plural pull-down paths.

21. The system of claim 20 wherein selected ones of said plural pull-down paths are characterized by said gated transistors being in series with a resistive element.

22. The system of claim 20 further comprising a system signal generator having a system signal and wherein each of said plural triggering networks has an output signal-determinative input signal responsive to said system signal and said plural pull-down paths are disabled in response to assertion of said system signal on said output signal-determinative input signals.

23. The system of claim 22 wherein an inverted clock signal derived from said clock-derived signal is supplied to a selected set of said plural triggering networks.

24. The system of claim 22 wherein said triggering networks are D flip-flops.

25. The system of claim 22 wherein said monolithic integrated circuit is fabricated by a CMOS technology.

26. The system of claim 22 further comprising a trim register having a data signal supplied to said digital-to-analog converter.

27. The system of claim 22 wherein said system signal is a WRITE signal.