Integrated driver for display implemented with active addressing technique

• US 5,546,102 A
• Filed: 06/07/1995
• Issued: 08/13/1996
• Est. Priority Date: 04/01/1991
• Status: Expired due to Term

• Current Assignee: InFocus Corporation (Lap-Shun Hui, MBA)
• Original Assignee: InFocus Corporation (Lap-Shun Hui, MBA)
• Inventors: Scheffer, Terry J., Clifton, Benjamin R.
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): Mengistu, Amare
• Application Number:
  US08/484,433
• Time in Patent Office: 433 Days
• Field of Search: 345/87, 345/94, 345/98, 345/100, 395/55, 395/56
• US Class Current: 345/100
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3625 using active addressing

Abstract

Integrated driver circuitry including row and column signal generators addresses faster responding liquid crystal display panels (LCDs) so that video rate, high information content LCDs having time constants on the order of 50 ms or less are perceived as having improved contrast by limiting peak voltage levels across the pixels. In a preferred embodiment, a row signal generator includes a row signal function generator and row driver circuitry including a level shifter that delivers to each of the row electrodes a signal level corresponding to the row signal value at a time interval of a frame period. A column signal generator applies to each of the column electrodes a column signal having an amplitude that is determined by the row signals causing selections at a particular time interval and by pixel input data components of corresponding pixels defined by the overlap of the row and column electrodes. The amplitudes of multiple column signals are generated by multiple retrievals distributed over the frame period of each of the pixel input data components stored in memory sites.

Claims

1. Integrated driver circuitry for addressing a video display system in which overlapping row and column electrodes positioned on opposite sides of an rms-responding material form an array of pixels that display pixel information states in response to video signal control and pixel input data provided by a video signal controller, the integrated driver circuitry, comprising:

a row signal generator including a row signal function generator and row driver circuitry,

the row signal function generator generating a set of row signals for driving corresponding row electrodes during a frame period that is divided into time intervals, the row signal function generator responsive to video signal control data provided by the video signal controller to provide for each row electrode during each time interval a row signal value representing a row function at the time interval, the row function characterized in that each one of the row signals in the set causes multiple selections of the corresponding row electrode, the multiple selections take place during different ones of the time intervals and being distributed over the frame period, and each of the row signals provides a number of the time intervals over the frame period that is less than an exponential function of the number of row electrodes, and

the row driver circuitry including a level shifter that delivers to each of the row electrodes a signal level corresponding to the row signal value at the time interval; and

a column signal generator responsive to the video signal control and pixel input data and the row signal values representing the row function to generate for each time interval a column signal for driving each of the column electrodes, each column signal having an amplitude that is derived from a transformation of the values of row signals causing selections and the video pixel input data related to the corresponding pixels;

the amplitudes of multiple column signals being derived by contributions of the multiple selections by each one of the row signals in the set that are distributed over the frame period so as to reduce a frame response of the display.

2. The drive circuitry of claim 1 in which the row signals are normalized to a common value.

3. The drive circuitry of claim 1 in which the row signals are orthogonal to one another.

4. The drive circuitry of claim 1 in which the row function generator includes a pseudo-random binary sequence generator that generates data corresponding to the row signals.

5. The drive circuitry of claim 1 in which the row function generator includes a read only memory that stores data corresponding to the row signals.

6. The system of claim 1 in which the column signal generator further includes a memory storing information representative of the pixel input data.

7. The drive circuitry of claim 6 further including a set of electrode driver circuits that receive and condition at least one of the row signals and the column signals for driving the corresponding electrodes, and in which more than one of the column signal generator, the row signal generator, the memory, and the electrode driver circuits is implemented on a single integrated circuit.

8. The drive circuitry of claim 1 in which the transformation is a correlation function that includes a summing process and a multiplying process.

9. The drive circuitry of claim 1 in which the transformation derives the amplitude of each column signal by computing the sum of the products of the amplitude of each row signal causing a selection times the pixel information state of the corresponding pixel.

10. The drive circuitry of claim 9 in which the computation of the sum of the products is implemented with digital circuitry in the column signal generator.

11. The drive circuitry of claim 9 in which the computation of the sum of the products is implemented with analog circuitry in the column signal generator.

12. The drive circuitry of claim 1 in which the transformations are generated for each column signal by a plurality of exclusive-or gates whose outputs are summed by a digital summing network so as to provide a digital representation that is proportional to the number of matching elements of the row signal and logic states of the selected pixels in each column, and in which the system further comprises converting means for converting the digital representation to an analog signal.

13. The drive circuitry of claim 12 in which the converting means comprises a digital-to-analog converter.

14. The drive circuitry of claim 12 in which the converting means includes an analog multiplexer that provides a selected one of a plurality of discrete voltage levels.

15. Integrated driver circuitry for addressing column electrodes of a video display system in which overlapping row and column electrodes positioned on opposite sides of an rms-responding material provide an array of pixels that display pixel information states in response to a video signal provided by a video signal controller and to row signals provided by a row signal generator, the video signal having control components and pixel input data components, the pixel input data components representing the data to be displayed by the pixels, and the row signals applied to and causing multiple selections of corresponding row electrodes during a frame period that is subdivided into time intervals, the row signals representing row signal function vectors, and the multiple selections being distributed over the frame period, comprising:

storage sites for receiving and storing the pixel input data components;

row signal input that receives the row signals;

a column signal generator for generating and applying a column signal to each of the column electrodes, the column signal generator communicating with the storage sites to receive the pixel input data components according to the control components, communicating with the row signal input to receive according to the control components the row signal function vectors in sequence to generate multiple column signals, and during the frame period generating for each column a column signal having an amplitude that is determined by the row signals causing selections at a particular time interval and by the pixel input data components of the corresponding pixels; and

the amplitudes of multiple column signals being generated by multiple retrievals distributed over the frame period of each of the pixel input data components stored in the storage sites.

16. The drive circuitry of claim 15 in which at least some of the row signals have amplitudes that include two nonzero signal levels to effect the multiple selections of the corresponding row electrodes and in which the amplitude of each column signal during each time interval is proportional to a sum of exclusive-or products of logic levels representative of the two nonzero signal levels of the row signals and logic levels representative of the pixel input data components of pixels defined by the corresponding row electrodes.

17. The drive circuitry of claim 22 in which the storage sites are subdivided into first and second sets of storage sites, the first set of storage sites in data communication with a video source to receive the pixel input data components and the second set of storage sites responding to the video signal controller to receive by transfer the pixel input data components previously stored in the first set of memory sites to generate the column signals.

18. The drive circuitry of claim 15, further comprising circuitry for randomly re-ordering a plurality of the row signals before they are applied to the row electrodes.

19. The drive circuitry of claim 15, further comprising circuitry for inverting the amplitudes of a certain proportion of the row signals.

20. The drive circuitry of claim 15 in which the amplitude of each column signal is determined by a plurality of exclusive-or gates whose outputs are summed by a digital summing network so as to provide a digital representation that is proportional to the number of matching elements of the row signal and logic states of the selected pixels defined by each column electrode, and in which the system further comprises a signal converter for converting the digital representation to an analog signal.

21. The drive circuitry of claim 15 in which the amplitude of each column signal is determined by computing the sum of the products of the amplitude of each row signal causing a selection times the pixel information state of the corresponding pixel.

22. The drive circuitry of claim 21 in which the computation of the sum of the products is implemented with digital circuitry in the column signal generator.

23. The drive circuitry of claim 21 in which the computation of the sum of the products is implemented with analog circuitry in the column signal generator.