Flexible switching hub for a communication network
First Claim
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1. A communication subsystem comprising:
- a central processing unit (CPU);
a communication segment comprising;
a switched hub circuit comprising a plurality of serial communication ports, each serial communication port comprising;
a transmit first-in-first-out buffer (FIFO);
a receive FIFO;
a transmit direct memory access (DMA) circuit;
a receive DMA circuit; and
a communication control circuit;
a dynamic random access memory (DRAM) subsystem, the DRAM subsystem comprising a plurality of virtual transmit FIFOs (VTFs), each VTF corresponding to a serial communication port of the plurality of serial communication ports, each VTF comprising a plurality of frame buffers; and
a system interconnect bus coupling the switched hub circuit, the DRAM subsystem and the CPU.
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Abstract
A communication system with switched hub is disclosed including a set of communication ports that transfer inbound and outbound communication frames over corresponding serial communication links. The communication ports determine a destination port for each incoming communication frame and perform interleaved transfers of the incoming communication frames to a set of virtual transmit first-in first-out (FIFO) memories that buffer communication frames for outbound transfer. The mechanism disclosed enables fast and efficient switching of the inbound frames to corresponding outbound ports.
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Citations
13 Claims
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1. A communication subsystem comprising:
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a central processing unit (CPU); a communication segment comprising; a switched hub circuit comprising a plurality of serial communication ports, each serial communication port comprising; a transmit first-in-first-out buffer (FIFO); a receive FIFO; a transmit direct memory access (DMA) circuit; a receive DMA circuit; and a communication control circuit; a dynamic random access memory (DRAM) subsystem, the DRAM subsystem comprising a plurality of virtual transmit FIFOs (VTFs), each VTF corresponding to a serial communication port of the plurality of serial communication ports, each VTF comprising a plurality of frame buffers; and a system interconnect bus coupling the switched hub circuit, the DRAM subsystem and the CPU. - View Dependent Claims (2, 3, 4, 5)
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6. A communication method comprising the steps of:
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(A) receiving a communication frame in a receive first-in-first-out buffer (FIFO) of a source port; (B) determining a destination port for the communication frame received; (C) transferring the communication frame received to a virtual transmit FIFO (VTF) corresponding to the destination port using a receive direct memory access (DMA) circuit, the communication frame being stored in frame buffers of the VTF in order of arrival with respect to communication frames from different source ports being sent to the destination port, the communication frame and the communication frames from different source ports being interleaved in the VTF; and (D) transferring a topmost frame buffer of the VTF to a transmit FIFO in the destination port using a transmit DMA circuit. - View Dependent Claims (7, 8, 9, 10)
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11. A communication system comprising:
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a plurality of communication agents; a communication subsystem coupled to the plurality of communication agents, the communication subsystem comprising; a plurality of central processing unit (CPU) subsystems; a plurality of communication segments, a communication segment comprising; a switched hub circuit comprising; a plurality of serial communication ports, each serial communication port comprising a transmit first in first out buffer (FIFO), a receive FIFO, a transmit direct memory access (DMA) circuit, and a receive DMA circuit; and a plurality of parallel communication ports, each parallel communication port comprising a transmit FIFO, a receive FIFO, a plurality of transmit DMAs, a plurality of receive DMAs, and a bus interface circuit; a dynamic random access memory (DRAM) subsystem comprising; a plurality of virtual transmit FIFOs (VTFs), each VTF corresponding to a serial communication port of the plurality of serial communication ports, each VTF comprising a plurality of frame buffers; a broadcast memory structure; and a control memory block; and a system interconnect bus coupling the plurality of CPU subsystems and the plurality of communication segments. - View Dependent Claims (12, 13)
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Specification