Method and apparatus for communicating between a plurality of subcomponents

• US 5,546,396 A
• Filed: 02/05/1993
• Issued: 08/13/1996
• Est. Priority Date: 02/05/1992
• Status: Expired due to Fees

• Current Assignee: Sextant Avionique
• Original Assignee: Sextant Avionique
• Inventors: Jaeger, Christian, Clauzel, Yves
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US08/014,429
• Time in Patent Office: 1,285 Days
• Field of Search: 370/85.1, 370/85.11, 370/85.9, 370/85.7, 370/94.1, 370/95.1, 370/60, 370/84, 370/85.13
• US Class Current: 370/464
• CPC Class Codes: G06F 13/372 using a time-dependent priority, e.g. individually loaded time counters or time slot

Abstract

A processor system and communications processor between a plurality of sub-components is described. To each sub-component of equipment is associated at least one logical channel that is associated with at least one physical channel. Each sub-component addressing only the logical channels that it is associated with, and the various physical channels being time multiplexed on an internal communications bus (BCI). The system has particular application to systems of radio-communication or of embarked navigation.

Claims

1. A process for the transmission of information data between a plurality of sub-components, in which each sub-component is associated with at least one logical channel, wherein each logical channel is associated with at least one physical channel, each sub-component addressing said logical channel with which it is associated, wherein different physical channels are time multiplexed on an internal communication bus, wherein at least one sub-component is further coupled with at least one input/output line, wherein said information data generated by a sub-component on said input/output line is re-transmitted on said internal communication bus to other sub-components, and said information data received by said sub-component on said input/output line is re-transmitted on said internal communication bus to said other sub-components.

2. A process for the transmission of information data between a plurality of sub-components, in which each sub-component is associated with at least one logical channel, wherein each logical channel is associated with at least one physical channel, each sub-component addressing said logical channel with which it is associated, wherein different physical channels are time multiplexed on an internal communication bus, wherein at least one sub-component is further coupled to at least one input/output line, said input/output lines functioning at a frequency that is a sub-multiple of a basic frequency, the functioning frequency of said internal communication bus being a multiple of said basic frequency.

3. A communication system for equipment comprising a plurality of sub-components in which at least one of said plurality of said sub-components includes at least one communication line, said communication line functioning at a frequency that is a sub-multiple of a basic frequency, said basic frequency being the same for each communication line, each sub-component further including at least one communications processor connected with said communication line, said communications processor of each sub-component being further coupled between each other by an internal communication bus on which are multiplexed a plurality of physical channels at a multiple frequency of said basic frequency.

4. The communication system according to claim 3 wherein at least one sub-component comprises one central unit and one memory coupled by a local bus, said communications processor of said sub-component being further coupled to said local bus.

5. The communications system according to claim 4 wherein each central unit is designed to exchange with said communications processor via said local bus information data linked to numbers of logical channels independent of the physical channels, said communications processor being designed to associate one logical channel of the central unit to one physical channel of the internal communication bus.

6. A communication system for equipment comprising a plurality of sub-components in which at least one of said plurality of said sub-components includes at least one communication line, said communication line functioning at a frequency that is a sub-multiple of a basic frequency, said basic frequency being the same for each communication line, each sub-component further including at least one communications processor connected with said communication line, said communications processor of each sub-component being further coupled between each other by an internal communication bus on which are multiplexed a plurality of physical channels at a multiple frequency of said basic frequency, wherein the internal communication bus is one link to a plurality of cables, a first cable carrying a synchronization signal of said basic frequency, a second cable carrying a clock signal indicating the changes of physical channels, and the other cables carrying information data.

7. The communication system according to claim 6 wherein each communications processor has a counter of physical channels capable of being incremented by said clock signal and of being reset at zero by said synchronization signal for the determination of physical channel numbers.

8. The communication system according to claim 7 wherein each communications processor has an internal clock and a phase generator in order to link the incrementation input of its physical channel counter, either to a clock signal of said internal communication bus or to its internal clock, said phase generator for providing a synchronization signal, and means being provided in order to selectively link up the synchronization signal of said phase generator with said synchronization cable of said internal communication bus, one of said communications processors of said system having its internal clock coupled to said clock cable of said internal communication bus, and synchronization signal of its phase generator coupled to said synchronization cable of said internal communication bus, and each processor having said incrementation input of its physical channel counter coupled to said clock cable of said internal communication bus and its input of zero resetting coupled to said synchronization cable of said internal communication bus.

9. A communications processor between a plurality of sub-components of an equipment comprising:

a first linkage means coupled to a first sub-component of said equipment and at least one of a number of logical channels, said first linkage means designed to exchange information data between said first sub-component and said at least one of a number of logical channels;

a second linkage means coupled to said first sub-component and at least a second sub-component of said equipment, said second linkage means designed to exchange said information data between said first sub-component and said second sub-component during a period of successive occurrences of a physical channel, a group of physical channels following each other at one frequency and according to a predetermined order; and

association means to associate each logical channel to at least one physical channel.

10. The communication processor according to claim 9 wherein said linkage means to said first sub-component comprises a linkage unit to a central unit of said first sub-component.

11. The communication processor according to claim 19 wherein said first linkage means coupled to the first sub-component comprises direct access means to a memory of said first sub-component.

12. The communications processor according to claim 11 wherein said direct access means comprises means for forming an address of said memory of said first sub-component at least according to said number of the logical channel associated with said information data, a memory containing information on the functioning mode of said logical channel, and means for reading or writing said information data to said address according to said information on the functioning mode of the logical channel.

13. The communications processor according to claim 12 wherein said address formation means are designed to form said address equally according to one part of the exchanged information data.

14. The communications processor according to claim 9 wherein said first linkage means comprises one exchange memory in which each memory zone is allocated to one logical channel, said first linkage means is designed to contain either the information data originating from said first sub-component that is destined through said second linkage means to the second sub-component or information data originating from said second linkage means and destined for the first sub-component, according to the functioning mode of the logical channel under consideration and to contain an information of request/fulfillment.

15. The communications processor according to claim 14, comprising means for giving a first value to said information of request/fulfillment when a word originating from said second linkage means has been placed in said memory zone at the disposal of said first linkage means or when a word placed in said memory zone by said first linkage means has been read for transmission to said second linkage means, according to the functioning mode of said logical channel associated with said memory zone, and means for giving a second value to said information of request/fulfillment when the word put at the disposal of said first linkage means has been read by the first linkage means or, respectively, when a new word has been placed in said memory zone by said first linkage means for transmission to said second linkage means.

16. The communications processor according to claim 15 wherein said linkage means to said first sub-component comprises an address counter in order to successively address each memory zone of said exchange memory, said means for reading said memory zone, said means for analyzing said value of the information of request/fulfillment contained in said zone and for the stopping of said address counter as said information of request/fulfillment has its first value, and means in order to, in that case, and according to the functioning mode of said logical channel associated with memory zone, to place in said zone a new word in view of its transmission to said linkage means to said second sub-component or to transmit to the first sub-component the word read, and in order to give its second value to said information of request/fulfillment.

17. The communications processor according to claim 14 wherein said linkage means to said first sub-component comprises one configuration memory of said logical channels wherein every zone is linked to a logical channel by said linkage means to said first sub-component, said configuration memory being addressed in synchronism with said exchange memory.

18. The communications processor according to claim 9 wherein said association means comprises one physical channel counter and one association memory where each memory zone is addressed by said physical channel counter, and is designed to contain at least the number of a logical channel associated with the corresponding physical channel at the value of said counter.

19. The communications processor according to claim 18 wherein each memory zone of said association memory is moreover designed to contain an information indicating if said physical channel corresponding to said zone is actually associated with a logical channel.

20. The communications processor according to claim 18 wherein each memory zoned of said association memory is moreover designed to contain an information on the functioning mode of the logical channel associated with said physical channel corresponding to said value of said counter.

21. The communications processor according to claim 9 wherein said linkage means to said second sub-component comprises a context memory wherein each zone is linked to a logical channel, and is designed to contain at least one word in the course of processing on the corresponding logical channel.

22. The communications processor according to claim 21 wherein each memory zone of said context memory is further provided with a memory location forming a counter in order to contain a position of a next bit to be processed in the word in the course of said processing.

23. The communications processor according to claim 21 wherein each memory zone of said context memory additionally comprises a location of memory capable of receiving said value of said next bit to be transmitted or of the last bit received.

24. The communications processor according to claim 9 wherein said linkage means to said second sub-component comprises a processing unit designed to receive from a context memory, at each occurrence of a physical channel, data related to the context of said logical channel associated with that physical channel, said data comprising at least one word in the course of processing on said logical channel, and a linkage interface between said processing unit and said second sub-component, said processing unit being designed to update at each of said occurrences, said data relating to the context according to at least one information exchange with said interface.

25. The communications processor according to claim 24 wherein said linkages between said processing unit and said memories are parallel linkages, and said linkage between said processing unit and said interface is a serial linkage.

26. The communications processor according to claim 24 wherein said memories are addressed by an output register of an association memory that itself is addressed by a physical channel counter.

27. The communications processor according to claim 9 wherein said linkage means to said second sub-component comprises a processing unit linked by said linkage means to said first sub-component through an intermediary means of an exchange memory wherein each memory zone is linked to a logical channel and is designed to contain at least one word of information to be exchanged with said linkage means to said first sub-component, and an request/fulfillment information, and a linkage means between said processing unit and said second sub-component, said processing unit being designed, when said request/fulfillment information has a certain value, to exchange a word of information with said exchange memory, and to give another value to said request/fulfillment information, and, according to the functioning mode of the logical channel, to transmit said exchanged word to said interface or to receive from said interface a new word to be exchanged.