Signal intercept system and method

• US 5,546,398 A
• Filed: 07/23/1993
• Issued: 08/13/1996
• Est. Priority Date: 07/23/1993
• Status: Expired due to Fees

• Current Assignee: NTSE Communications Incorporated
• Original Assignee: NTSE Communications Incorporated
• Inventors: Sams, Gary, Condit, Mario, Pattikonda, Ramakhrisna, Tucker, Michel H., Hennessey, Kathleen
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Nguyen, Chau T.
• Application Number:
  US08/096,665
• Time in Patent Office: 1,117 Days
• Field of Search: 379/112, 379/115, 379/230, 379/229, 379/201, 379/207, 370/110.1, 370/60, 370/85.13, 370/85.14, 370/68.1, 370/94.1
• US Class Current: 370/389
• CPC Class Codes: H04Q 3/0025 Provisions for signalling

Abstract

A signal intercept system intercepts an international calling frame, modifies a specific set of bits and then retransmits the frame in real time. The signal intercept system includes a communications processor and a signalling link interface. In one arrangement, the signalling link interface includes two intercept and transmit connectors and a coprocessor connector. In one arrangement, the communications processor includes a computer and a communications coprocessor. The computer maintains a data base with tables of such data as invalid calling card numbers. A computer program initializes and starts the communications coprocessor which handles high speed signal capture, manipulation and high speed signal retransmission. The communications coprocessor also interacts with the computer'"'"'s data base to alter table parameters.

Claims

1. A real time signal intercept system for installation in a signalling link between a first signal point which transmits first high speed data signals and a second signal point which would receive the first high speed data signals except they are intercepted by the signal intercept system, comprising in combination:

a computer which processes data received by the signal intercept system in the form of signals from the first signal point;

a communications coprocessor operably connected to the computer;

a signalling link interface which intercepts the first high speed data signals transmitted from the first signal point onto the signalling link and then directs the intercepted signals to the communications coprocessor and transmits processed first high speed data signals received from the communications coprocessor onto the signalling link to the second signal point, wherein the second signal point receives the processed first high speed data signals, and wherein the communications coprocessor captures the first high speed data signals received from the signalling link interface and presents captured first high speed data in a form acceptable to the computer, converts processed first high speed data from the computer into the processed first high speed data signals in a form acceptable to the signalling link and transmits the first high speed data signals to the signalling link interface.

2. A signal intercept system according to claim 1 wherein the signalling link interface comprises in combination:

an intercept connector which intercepts the first high speed data signals transmitted on the signalling link from the first signal point;

a coprocessor connector which directs the intercepted first high speed data, signals from the receive connector to the communications coprocessor and receives the processed first high speed data signals from the communications coprocessor; and

a transmit connector which transmits the processed first high speed data signals received by the coprocessor connector from the communications coprocessor onto the signalling link to the second signal point.

3. A signal intercept system according to claim 1 wherein the signalling link interface also intercepts second high speed data signals transmitted from the second signal point onto the signalling link intended for the first signal point and directs the intercepted second high speed data signals to the communications coprocessor and transmits processed second high speed data signals received from the communications coprocessor onto the signalling link to the first signal point.

4. A signal intercept system for installation in a signalling link between a first signal point which transmits first high speed data signals and a second signal point which would receive the first high speed data signals except they are intercepted by the signal intercept system, comprising in combination:

a computer which processes data received by the signal intercept system in the form of signals from the first signal point;

a communications coprocessor operably connected to the computer;

a signalling link interface which intercepts the first high speed data signals transmitted from the first signal point onto the signalling link and then directs the intercepted signals to the communications coprocessor and transmits processed first high speed data signals received from the communications coprocessor onto the signalling link to the second signal point, wherein the second signal point receives the processed first high speed data signals, and wherein the communications coprocessor captures the first high speed data signals received from the signalling link interface and presents captured first high speed data in a form acceptable to the computer, converts processed first high speed data from the computer into the processed first high speed data signals in a form acceptable to the signalling link and transmits the first high speed data signals to the signalling link interface, and wherein the signalling link interface also intercepts second high speed data signals transmitted from the second signal point onto the signalling link intended for the first signal point and directs the intercepted second high speed data signals to the communications coprocessor and transmits processed second high speed data signals received from the communications coprocessor onto the signalling link to the first signal point, and wherein the signalling link interface comprises in combination;

a first connector which intercepts the first high speed data signals transmitted on the signaling link from the first signal point;

a second connector which intercepts the second high speed data signals transmitted on the signaling link from the second signal point; and

a coprocessor connector which directs the intercepted first high speed data signals from the first connector and the second high speed data signals from the second connector to the communications coprocessor and for receiving the processed first high speed data signals and the processed second high speed data signals from the communications coprocessor;

wherein the first connector also transmits the processed second high speed data signals received by the coprocessor connector from the communications coprocessor onto the signalling link to the first signal point and the second connector transmits the processed first high speed data signals received by the coprocessor connector from the communications coprocessor onto the signalling link to the second signal point.

5. A method for modifying selected data transmitted as signals on a signaling link between a first signal point and a second signal point in real time, comprising in combination the steps of:

intercepting the data signals transmitted from the first signal point;

converting the intercepted selected data signals into data of a form acceptable for data processing;

processing converted selected data wherein the selected data is modified;

converting the modified selected data into data signals in a form acceptable by the signalling link; and

transmitting the converted modified selected data signals along with any data signals which were not selected to the second signal point.

6. A method for modifying selected data transmitted as signals on a signaling link between a first signal point and a second signal point for use with a telephone system having dialed digits and gate numbers, which telephone system uses a Signalling System 7 protocol, comprising in combination the steps of:

intercepting the data signals transmitted from the first signal point;

converting intercepted selected data signals into data of a form acceptable for data processing;

processing the converted selected data wherein the selected data is modified;

converting the modified selected data into data signals in a form acceptable by the signalling link; and

transmitting the converted modified selected data signals along with any data signals which were not selected to the second signal point, wherein the selected data is transmitted in packets consisting of frames, and the step of processing the converted selected data uses a communications controller and comprises in combination the steps of;

testing for an end of a receive frame;

if the end of a receive frame is detected, resetting the communications controller to receive the next frame; and

then receiving the next frame;

begin timing for a predetermined amount of time;

if the end of the receive frame is not received, then testing for an end of a transmit frame;

if the end of a transmit frame is not detected, starting the step of processing converted data again;

if the end of a transmit frame is detected, resetting the communications controller for transmitting;

testing for expiry of the predetermined amount of time;

if the time has not expired, transmitting a fill-in status unit or a link status signal unit; and

then starting over with testing for an end of a receive frame;

if the time has expired, transmitting a message signal unit;

testing if the frame ended is an initial address message;

if the frame is not an initial address message, then starting over with testing for an end of receipt of the selected data;

if the frame is an initial address message, getting the dialed digits; and

then getting the gate number; and

then changing the gate number; and

starting over with testing for an end of a receive frame.

7. A method for modifying selected data transmitted as signals on a signaling link between a first signal point and a second signal point for use with a telephone system which a Signalling System 7 protocol, comprising in combination the steps of:

intercepting the data signals transmitted from the first signal point;

converting intercepted selected data signals into data of a form acceptable for data processing;

processing the converted selected data wherein the selected data is modified;

converting the modified selected data into data signals in a form acceptable by the signalling link; and

transmitting the converted modified selected data signals along with any data signals which were not selected to the second signal point, wherein the selected data is transmitted in packets consisting of frames, wherein the step of processing the converted data uses a communications controller having Channel A receive and transmit registers, Channel B receive and transmit registers, a transmit buffer, a receive buffer and a direct memory access controller, and wherein the selected data is transmitted in packets consisting of frames, begun by a receive frame and ended with a transmit frame, the step comprising in combination the steps of;

initializing the receive and transmit registers with values for desired operation;

initializing two separate buffers and the direct memory access controller for transmit and receive channels;

opening the channels for intercepting the signals and receive the receive frame to receive channel;

transmitting the first frame with desired delay;

testing for end of receive frame;

if the end of receive frame is detected, resetting the receive registers;

initializing the receive channel to receive the next frame;

loading the timer with a predetermined amount of time;

if the end of receive frame is not detected, testing for end of transmit frame;

if end of transmit frame is not detected, starting the step of processing the converted data;

if the end of transmit frame is detected, resetting the transmit registers;

testing for timer expiry;

if the timer has not expired, initializing to transmit fill-in-signal-unit or link-status-signal unit and then starting over;

if the timer has expired, initializing to transmit message signal unit;

testing if the frame ended is an initial address message or TCAP request;

if the frame is not initial address message or TCAP request, starting over;

if the frame is an initial address message, getting the dialed digits the gate number and other digits, and

looking up the database tables to see if the gate number has to be changed for rerouting purposes;

if so, getting the gate number from the database tables and then changing the gate number and starting over;

if the frame is a TCAP request component containing calling card dialed digits information, storing the calling card information in calling card table and informing the main processor of the new calling card number;

checking the exception calling card table to see if the current called card is a valid card;

if so, make no changes;

if the current called number is found in the exception table, voiding the request by changing the calling card number to a non-existent number or rerouting the related call to an operator or law enforcement authority;

making the main processor periodically process the calling card table to recognize the patterns for exception calls and store the exception calling numbers in the exception calling card table and starting over;

adjusting the timing of channels so that the information processing operation lies between the receive channel and transmit channel operation and none of these three operations conflict as they are operating simultaneously.

8. A real time signal intercept system for use with a computer and installation in a signalling link between a first signal point which transmits first high speed data signals and a second signal point which would receive the first high speed data signals except they are intercepted by the signal intercept system, comprising in combination:

a communications coprocessor operably connected to the computer;

a signalling link interface which intercepts the first high speed data signals transmitted from the first signal point onto the signalling link and then directs the intercepted signals to the communications coprocessor and transmits processed first high speed data signals received from the communications coprocessor onto the signalling link to the second signal point, wherein the second signal point receives the processed first high speed data signals, and wherein the communications coprocessor captures the first high speed data signals received from the signalling link interface and presents captured first high speed data in a form acceptable to the computer, converts processed first high speed data from the computer into the processed first high speed data signals in a form acceptable to the signalling link and transmits the first high speed data signals to the signalling link interface.

9. A signal intercept system according to claim 8 wherein the signalling link interface comprises in combination:

an intercept connector which intercepts the first high speed data signals transmitted on the signalling link from the first signal point;

a processor connector which directs the intercepted first high speed data signals from the receive connector to the communications processor and receives the processed first high speed data signals from the communications processor; and

a transmit connector which transmits the processed first high speed data signals received by the processor connector from the communications processor onto the signalling link to the second signal point.

10. A signal intercept system according to claim 8 wherein the signalling link interface also intercepts second high speed data signals transmitted from the second signal point onto the signalling link intended for the first signal point and directs the intercepted second high speed data signals to the communications processor and transmits processed second high speed data signals received from the communications processor onto the signalling link to the first signal point.

11. A signal intercept system for use with a computer and installation in a signalling link between a first signal point which transmits first high speed data signals and a second signal point which would receive the first high speed data signals except they are intercepted by the signal intercept system, comprising in combination:

a communications coprocessor operably connected to the computer;

a signalling link interface which intercepts the first high speed data signals transmitted from the first signal point onto the signalling link and then directs intercepted signals to the communications coprocessor and transmits the processed first high speed data signals received from the communications coprocessor onto the signalling link to the second signal point, wherein the second signal point receives the processed first high speed data signals, and wherein the communications coprocessor captures the first high speed data signals received from the signalling link interface and presents captured first high speed data in a form acceptable to the computer, converts processed first high speed data from the computer into the processed first high speed data signals in a form acceptable to the signalling link and transmits the first high speed data signals to the signalling link interface, wherein the signalling link interface also intercepts second high speed data signals transmitted from the second signal point onto the signalling link intended for the first signal point and directs intercepted second high speed data signals to the communications processor and transmits processed second high speed data signals received from the communications processor onto the signalling link to the first signal point, and wherein the signalling link interface comprises in combination;

a first connector which intercepts the first high speed data signals transmitted on the signaling link from the first signal point;

a second connector which intercepts the second high speed data signals transmitted on the signaling link from the second signal point; and

a processor connector which directs the intercepted first high speed data signals from the first connector and the second high speed data signals from the second connector to the communications processor and for receiving the processed first high speed data signals and the processed second high speed data signals from the communications processor;

wherein the first connector also transmits the processed second high speed data signals received by the processor connector from the communications processor onto the signalling link to the first signal point and the second connector transmits the processed first high speed data signals received by the processor connector from the communications processor onto the signalling link to the second signal point.