Semiconductor memory device with error self-correction system starting parity bit generation/error correction sequences only when increase of error rate is forecasted

• US 5,546,410 A
• Filed: 08/02/1994
• Issued: 08/13/1996
• Est. Priority Date: 08/03/1993
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Monden, Junji, Ando, Manabu
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US08/284,204
• Time in Patent Office: 742 Days
• Field of Search: 371/37.4, 371/40.1, 371/40.2, 371/40.3, 371/40.4, 371/50.1
• US Class Current: 714/764
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

A semiconductor memory device has a built-in error correction system for correcting undesirably inverted data bits, and the built-in error correction system starts a parity bit generating sequence and an error correcting sequence only when increase of error rate is forecasted, thereby increasing the access speed without sacrifice of the reliability.

Claims

1. A semiconductor memory device for selectively entering into a standard mode, an error correcting mode and an inspection bit generating mode, comprising:

a) a memory cell array having a plurality of addressable memory cells for respectively storing data bits, and forming a plurality of memory cell groups, said data bits being repeatedly rewritable and accessible externally of said semiconductor memory device without an error correction in said standard mode;

b) a plurality of addressable status cells selectively associated with said plurality of memory cell groups for respectively storing inspection bits indicative of correct states of said data bits stored in said plurality of memory cell groups;

c) an addressing system selectively making said plurality of addressable memory cells writable and readable in said standard mode, selectively making said plurality of memory cell groups and said plurality of addressable status cells readable and said plurality of addressable memory cells writable in said error correcting mode, and selectively making said plurality of memory cell groups readable and said plurality of addressable status cells writable in said inspection bit generating mode;

d) an interface unit enabled in said standard mode, and operative to receive new data bits from externally and to externally deliver the data bits read out from said memory cell array;

e) an inspecting and correcting system operative to check whether or not at least one data bit is inverted in the memory cells through comparison of the correct states with current states of said data bits respectively stored in said plurality of memory cell groups in said error correcting mode, said inspecting and correcting system being further operative to correct said at least one data bit in said error correcting mode, said inspecting and correcting system further being operative to generate said inspection bits through an inspection of the data bits stored in the associated memory cell groups in said inspection bit generating mode; and

f) a mode discriminator coupled to a port changeable in status externally of said semiconductor memory device, and operative to discriminate the status of said port to check whether to cause said semiconductor memory device to enter into said error correcting mode, said mode discriminator further discriminating another status of said port for causing said semiconductor memory device to enter into said inspection bit generating mode,

said mode discriminator being coupled to signal pins exclusively assigned to an instruction for entry into said inspection bit generating mode and an instruction for entry into said error correcting mode, said mode discriminator being responsive to said instruction for entry into said inspection bit generating mode for producing a first request signal for an inspection bit generating sequence, said mode discriminator being further responsive to said instruction for said entry into said error correcting mode for producing a second request signal for an error correcting sequence.

2. A semiconductor memory device for selectively entering into a standard mode, an error correcting mode and an inspection bit generating mode, comprising:

a) a memory cell array having a plurality of addressable memory cells for respectively storing data bits, and forming a plurality of memory cell groups, said data bits being repeatedly rewritable and accessible externally of said semiconductor memory device without an error correction in said standard mode;

b) a plurality of addressable status cells selectively associated with said plurality of memory cell groups for respectively storing inspection bits indicative of correct states of said data bits stored in said plurality of memory cell groups;

c) an addressing system selectively making said plurality of addressable memory cells writable and readable in said standard mode, selectively making said plurality of memory cell groups and said plurality of addressable status cells readable and said plurality of addressable memory cells writable in said error correcting mode, and selectively making said plurality of memory cell groups readable and said plurality of addressable status cells writable in said inspection bit generating mode;

d) an interface unit enabled in said standard mode, and operative to receive new data bits from externally and to externally deliver the data bits read out from said memory cell array;

e) an inspecting and correcting system operative to check whether or not at least one data bit is inverted in the memory cells through comparison of the correct states with current states of said data bits respectively stored in said plurality of memory cell groups in said error correcting mode, said inspecting and correcting system being further operative to correct said at least one data bit in said error correcting mode, said inspecting and correcting system further being operative to generate said inspection bits through an inspection of the data bits stored in the associated memory cell groups in said inspection bit generating mode; and

f) a mode discriminator coupled to a port changeable in status externally of said semiconductor memory device, and operative to discriminate the status of said port to check whether to cause said semiconductor memory device to enter into said error correcting mode, said mode discriminator further discriminating another status of said port for causing said semiconductor memory device to enter into said inspection bit generating mode

said mode discriminator being coupled to a first external control signal pin and a second external control signal pin, both serving as said port,

said mode discriminator including a first logic gate coupled to said first external control signal pin for producing an enable signal, a first one-shot pulse generator coupled to said second external control signal pin for producing a first one-shot pulse, a second logic gate coupled to said first one-shot pulse generator and enabled with said enable signal for producing a first request signal for said inspection bit generating mode from said first one-shot pulse, a second one-shot pulse generator coupled to said second external control signal pin for producing a second one-shot pulse, said first one-shot pulse generator and said second one-shot pulse generator being selectively enabled depending upon a potential level at said second external control signal pin, and a third logic gate coupled to said second one-shot pulse generator and enabled with said enable signal for producing a second request signal for said error correcting mode from said second one-shot pulse.

3. A semiconductor memory device for selectively entering into a standard mode, an error correcting mode and an inspection bit generating mode, comprising:

a) a memory cell array having a plurality of addressable memory cells for respectively storing data bits, and forming a plurality of memory cell groups, said data bits being repeatedly rewritable and accessible externally of said semiconductor memory device without an error correction in said standard mode;

b) a plurality of addressable status cells selectively associated with said plurality of memory cell groups for respectively storing inspection bits indicative of correct states of said data bits stored in said plurality of memory cell groups;

c) an addressing system selectively making said plurality of addressable memory cells writable and readable in said standard mode, selectively making said plurality of memory cell groups and said plurality of addressable status cells readable and said plurality of addressable memory cells writable in said error correcting mode, and selectively making said plurality of memory cell groups readable and said plurality of addressable status cells writable in said inspection bit generating mode;

d) an interface unit enabled in said standard mode, and operative to receive new data bits from externally and to externally deliver the data bits read out from said memory cell array;

e) an inspecting and correcting system operative to check whether or not at least one data bit is inverted in the memory cells through comparison of the correct states with current states of said data bits respectively stored in said plurality of memory cell groups in said error correcting mode, said inspecting and correcting system being further operative to correct said at least one data bit in said error correcting mode, said inspecting and correcting system further being operative to generate said inspection bits through an inspection of the data bits stored in the associated memory cell groups in said inspection bit generating mode; and

f) a mode discriminator coupled to a port changeable in status externally of said semiconductor memory device, and operative to discriminate the status of said port to check whether to cause said semiconductor memory device to enter into said error correcting mode, said mode discriminator further discriminating another status of said port for causing said semiconductor memory device to enter into said inspection bit generating mode,

said mode discriminator including means for producing a first request signal for entry into said inspection bit generating mode, a reference voltage generator coupled to a power voltage line for producing a reference voltage lower than a power voltage on said power voltage line, said power voltage line being supplied from said port with said power voltage level, a voltage comparator operative to compare said reference voltage with a predetermined threshold and to change a voltage level at the output node thereof when said reference voltage exceeds said predetermined threshold, and a one-shot pulse generator operative to produce a second request signal for said error correcting mode.

4. A semiconductor memory device for selectively entering into a standard mode, an error correcting mode and an inspection bit generating mode, comprising:

a) a memory cell array having a plurality of addressable memory cells for respectively storing data bits, and forming a plurality of memory cell groups, said data bits being repeatedly rewritable and accessible externally of said semiconductor memory device without an error correction in said standard mode;

b) a plurality of addressable status cells selectively associated with said plurality of memory cell groups for respectively storing inspection bits indicative of correct states of said data bits stored in said plurality of memory cell groups;

c) an addressing system selectively making said plurality of addressable memory cells writable and readable in said standard mode, selectively making said plurality of memory cell groups and said plurality of addressable status cells readable and said plurality of addressable memory cells writable in said error correcting mode, and selectively making said plurality of memory cell groups readable and said plurality of addressable status cells writable in said inspection bit generating mode;

d) an interface unit enabled in said standard mode, and operative to externally receive new data bits and to externally deliver the data bits read out from said memory cell array;

e) an inspecting and correcting system operative to check whether or not at least one data bit is inverted in the memory cells through comparison of the correct states with current states of said data bits respectively stored in said plurality of memory cell groups in said error correcting mode, said inspecting and correcting system being further operative to correct said at least one data bit in said error correcting mode, said inspecting and correcting system further being operative to generate said inspection bits through an inspection of the data bits stored in the associated memory cell groups in said inspection bit generating mode; and

f) a mode discriminator coupled to a port changeable in status externally of said semiconductor memory device, and operative to discriminate the status of said port to check whether to cause said semiconductor memory device to enter into said error correcting mode, said mode discriminator further discriminating another status of said port for causing said semiconductor memory device to enter into said inspection bit generating mode,

said semiconductor memory device entering into said inspection bit generating mode before a voltage level on a power voltage line is lower than a standard power voltage level and into said error correcting mode when said voltage level on said power voltage line is recovered from a low power voltage level to said standard power voltage level.