Digital phase lock loop having frequency offset cancellation circuitry

• US 5,546,433 A
• Filed: 03/21/1995
• Issued: 08/13/1996
• Est. Priority Date: 03/21/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Tran, Toan V., Henderson, Richard
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): NGUYEN, THUY LIEU T
• Application Number:
  US08/408,027
• Time in Patent Office: 511 Days
• Field of Search: 327/150, 327/159, 327/147, 375/376, 331/1 A, 331/1 R, 331/4, 331/16, 331/17, 331/25, 331/10, 364/162
• US Class Current: 375/376
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range

Abstract

A phase-lock loop (PLL) circuit can be locked on to a synthesizer frequency without decreasing the available range of the frequency differences which the PLL circuit can accommodate during a data receive mode. An analog-to-digital conveyer (ADC) receives an analog input signal and responds to a periodic clock signal by providing a corresponding digital output signal. A phase comparator is coupled to receive the ADC digital output signal and to provide a phase error signal which is representative of a phase error in the digital output signal. A filter accumulates the value of the phase error signal into a filter first register to generate a primary frequency error value. The filter further includes a filter second register for holding a secondary frequency error value (e.g., a value which corrects for an offset between a synthesizer frequency and the PLL free-running frequency). A primary digital-to-analog converter (DAC) converts a primary filter output value, which includes the primary frequency error value, to a corresponding primary analog output signal. A secondary DAC converts a secondary filter output value, which includes the secondary frequency error value from the filter second register, to a corresponding secondary analog output signal responsive to the secondary filter output value. The primary analog output signal and the secondary analog output signal the combined to provide a control signal to an oscillator that provides the clock signal to the ADC. The frequency of the clock signal is controlled by the control signal.

Claims

1. A phase lock loop circuit, comprising:

an analog-to-digital converter (ADC) that receives analog input signals and responds to a periodic clock signal by providing corresponding digital output signals;

a phase comparator coupled to receive the ADC digital output signals and which provides a phase error signal which is representative of a phase error in the digital output signals;

a filter, the filter including an integrator path that accumulates the value of the phase error signal into a first register to generate a primary frequency error value;

a second register for holding a secondary frequency error value;

a primary digital-to-analog converter (DAC) that converts a primary filter output value, which includes the primary frequency error value, to a corresponding primary analog output signal;

a secondary DAC, coupled to receive the secondary frequency error value from the secondary register and that converts the secondary frequency error value to a corresponding secondary analog output signal;

means for combining the primary analog output signal and the secondary analog output signal to generate an oscillator control signal;

an oscillator that provides the clock signal to the ADC, wherein the frequency of the clock signal is controlled by the oscillator control signal and

means for programming the secondary frequency error value to have a value equal to the primary frequency error value in the filter first register.

2. The phase lock loop circuit of claim 1, and further comprising a data selector having a first input to receive a reference analog signal and a second input to receive a data analog signal, and further having an output coupled to the ADC input, wherein the data selector responds to a data selector control signal by selectively providing one of the reference analog signal and the data analog signal at the data selector output.

3. The phase lock loop circuit of claim 1, wherein the filter further includes a proportional path and a derivative path, and wherein the primary filter output value includes an output from the proportional path and an output from the derivative path, in addition to the primary frequency error value.

4. A method for recovering data from an analog input data signal, the method comprising:

a) receiving the analog input data signal and responding to a periodic clock signal by providing corresponding digital output signals;

b) providing a phase error signal which is representative of a phase error in the digital output signals;

c) accumulating the value of the phase error signal into a filter first register to generate a primary frequency error value and providing a primary digital output signal whose value includes the primary frequency error value;

d) convening the primary digital output signal into a primary analog output value;

e) providing a secondary digital output value;

f) converting secondary digital output value into a secondary analog output value;

g) combining the primary analog output signal and the secondary analog output signal to generate an oscillator control signal; and

h) providing the clock signal, controlling the frequency of the clock signal with the oscillator control signal, wherein step e) comprises initially

i) performing steps a) through g) with a frequency synthesizer output signal in place of the analog input data signal; and

j) providing the primary frequency error value accumulated in step c) as the secondary digital output value.