Method and apparatus for parallel testing of memory
First Claim
1. A memory comprising:
- a number of memory groups, wherein each memory group includes;
a set of memory subgroups,a number of data bus drivers, wherein each data bus driver has a true input and a complement input and a true output and a complement output, the true and complement inputs being connected to a memory subgroup by at least one sense amplifier;
a true connection point, wherein the true output of one of the data bus drivers from each of the memory groups are connected together at the true connection point, wherein a wired configuration is created, wherein simultaneous addressing of a subset of the memory subgroups generates signals at the true and complement connection points;
a complement connection point, wherein the complement output of one of the data bus drivers from each of the memory groups are connected together at the complement connection point, wherein a wired configuration is created;
a data bus circuit having a true input connected to the true connection point and a complement input connected to the complement connection point and having a first circuit responsive to signals from the true and complement connection points created by simultaneously addressing of a subset of the memory subgroups, the first circuit having an output providing an indication of an error in addressing the subset of the memory subgroups during a test mode,wherein the data bus circuit includes a true output and a complement output and the first circuit includes a first transistor and a second transistor, the first transistor having a gate connected to the true output of the data bus circuit and the second transistor having a gate connected to the complement output of the data bus circuit, the first transistor having a drain connected to an upper power supply voltage, the second transistor having a source connected to the lower power supply voltage, and the source of the first transistor and the drain of the second transistor being connected to an output of the first circuit.
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Abstract
A memory includes a number of memory groups. Each memory group includes a set of memory subgroups and a number of data bus drivers, wherein each data bus driver has a true input and a complement input and a true output and a complement output. The true and complement inputs are connected to a memory subgroup by at least one sense amplifier. A true connection point also is included in the memory, and the true output of one of the data bus drivers from each of the memory groups are connected together at the connection point, and a "wired" configuration is created. In addition, the memory includes a complement connection point, wherein the complement output of one of the data bus drivers from each of the memory groups are connected together at the connection point, creating a "wired" configuration. The memory also has a data bus circuit with a true input connected to the true connection point and a complement input connected to the complement connection point and a first circuit. This data bus circuit is responsive to signals from the true and complement connection points created by the simultaneous addressing of multiple groups or a subset of the memory subgroups in testing mode. The first circuit has an output for providing an indication of an error in addressing of the multiple groups or the subset of the memory subgroups.
26 Citations
25 Claims
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1. A memory comprising:
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a number of memory groups, wherein each memory group includes; a set of memory subgroups, a number of data bus drivers, wherein each data bus driver has a true input and a complement input and a true output and a complement output, the true and complement inputs being connected to a memory subgroup by at least one sense amplifier; a true connection point, wherein the true output of one of the data bus drivers from each of the memory groups are connected together at the true connection point, wherein a wired configuration is created, wherein simultaneous addressing of a subset of the memory subgroups generates signals at the true and complement connection points; a complement connection point, wherein the complement output of one of the data bus drivers from each of the memory groups are connected together at the complement connection point, wherein a wired configuration is created; a data bus circuit having a true input connected to the true connection point and a complement input connected to the complement connection point and having a first circuit responsive to signals from the true and complement connection points created by simultaneously addressing of a subset of the memory subgroups, the first circuit having an output providing an indication of an error in addressing the subset of the memory subgroups during a test mode, wherein the data bus circuit includes a true output and a complement output and the first circuit includes a first transistor and a second transistor, the first transistor having a gate connected to the true output of the data bus circuit and the second transistor having a gate connected to the complement output of the data bus circuit, the first transistor having a drain connected to an upper power supply voltage, the second transistor having a source connected to the lower power supply voltage, and the source of the first transistor and the drain of the second transistor being connected to an output of the first circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory testing apparatus comprising:
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a plurality of data bus drivers, each data bus driver having a true input and a complement input connected to a set of memory cells and having a true output and a complement output, wherein the true outputs are connected together at a first point and the complement outputs are connected together at a second point; a data bus circuit, wherein the data bus circuit has a pair of inputs, a true input connected to the first point and a complement input connected to the second point, and a pair of outputs, a true output and a complement output; testing means for simultaneously accessing a plurality of memory cells in a memory, wherein each of the memory cells has the same data written into it for given output; and a sensing circuit connected to the true and complement output of the data bus circuit, the sensing circuit having an output, wherein an absence of error is indicated if the data from all of the memory cells accessed are identical, wherein the true and complement connection points are precharged and are both discharged upon the occurrence of an error.
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13. A memory testing apparatus comprising:
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a plurality of data bus drivers, each data bus driver having a true input and a complement input connected to a set of memory cells and having a true output and a complement output, wherein the true outputs are connected together at a first point and the complement outputs are connected together at a second point; a data bus circuit, wherein the data bus circuit has a pair of inputs, a true input connected to the first point and a complement input connected to the second point, and a pair of outputs, a true output and a complement output; testing means for simultaneously accessing a plurality of memory cells in a memory, wherein each of the memory cells has the same data written into it for given output; and a sensing circuit connected to the true and complement output of the data bus circuit, the sensing circuit having an output, wherein an absence of error is indicated if the data from all of the memory cells accessed are identical, wherein the data bus circuit is a data bus latch.
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14. A memory testing apparatus comprising:
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a plurality of data bus drivers, each data bus driver having a true input and a complement input connected to a set of memory cells and having a true output and a complement output, wherein the true outputs are connected together at a first point and the complement outputs are connected together at a second point; a data bus circuit, wherein the data bus circuit has a pair of inputs, a true input connected to the first point and a complement input connected to the second point, and a pair of outputs, a true output and a complement output; testing means for simultaneously addressing a plurality of memory cells in a memory, wherein each of the memory cells has the same data written into it for given output; and simultaneously reading data form the plurality of memory cells into a data bus circuit having a pair of inputs, a true input connected to the first point and a complement input connected to the second point, and a pair of output connected to a sensing circuit, the sensing circuit having an output, wherein an absence of error is indicated if the data from all of the memory cells accessed for a given output are identical;
wherein data is read from the plurality of memory cells by simultaneously addressing the plurality of memory cells and, wherein the data bus circuit includes a true output and a complement output and the first circuit includes a first transistor and a second transistor, the first transistor having a gate connected to the true output of the data bus circuit and the second transistor having a gate connected to the complement output of the data bus circuit, the first transistor having a drain connected to an upper power supply voltage, the second transistor having a source connected to the lower power supply voltage, and the source of the first transistor and the drain of the second transistors being connected to an output of the first circuit. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification