Single chip replacement upgradeable computer motherboard with enablement of inserted upgrade CPU chip

• US 5,546,563 A
• Filed: 01/04/1994
• Issued: 08/13/1996
• Est. Priority Date: 04/22/1991
• Status: Expired due to Term

• Current Assignee: Wistron Corporation
• Original Assignee: Acer, Inc.
• Inventors: Chuang, Te-Chih
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/177,648
• Time in Patent Office: 952 Days
• Field of Search: 395/400, 395/425, 395/500, 395/405, 395/497.01, 395/497.02, 395/497.03
• US Class Current: 703/27
• CPC Class Codes: G06F 13/4063 Device-to-bus coupling
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A computer system is made capable of accepting more than one type of central processor including a plurality of sockets for receiving more than one type of identification signal, a clock generator responsive to said identifying signal for generating clock signals for the identified type of processor, and means responsive to said identifying signal for disabling and enabling signal paths from the socket.

Claims

1. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a first socket, disposed on the circuit board, for receiving different types of CPU chips, wherein at least first and second of said different types of CPU chips drive a particular output signal on different first and second respective output pins, depending on the type of CPU chip;

an identifying circuit, disposed on the circuit board and coupled to said first socket, for identifying the type of CPU chip inserted in said first socket and for generating an identification signal in response to the identification;

a clock signal generator, disposed on the circuit board and coupled to said identifying circuit and to said first socket, responsive to said identification signal for generating clock signals compatible with the type of CPU chip in the first socket; and

an enabling circuit, disposed on the circuit board and coupled to said identifying circuit and said first socket, responsive to said identification signal for (a) enabling signals on said first output pin to be transmitted when one of said first type of CPU chips is in said first socket and (b) enabling signals on said second output pin to be transmitted when one of said second type of CPU chips is in said first socket, thereby allowing said particular output signal to be transmitted regardless of which one of said first and second types of CPU chips are in said first socket;

wherein said first socket includes engagement portions for said first and second output pins and said enabling circuit comprises;

an inverter having an input and an output, said input coupled to said identifying circuit;

a first tri-state gate having an input and an output and an enabling terminal, said input coupled to said engagement portion for said first output pin and said enabling terminal coupled to said identifying circuit; and

a second tri-state gate having an input and an output and an enabling terminal, said input coupled to said engagement portion for said second output pin, said enabling terminal coupled to said output of said inverter, and said output coupled to said output of said first tri-state gate through which said particular output signal is transmitted.

2. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a first socket, disposed on the circuit board, for receiving different types of CPU chips, wherein at least first and second of said different types of CPU chips drive a particular output signal on different first and second respective output pins, depending on the type of CPU chip;

an identifying circuit, disposed on the circuit board and coupled to said first socket, for identifying the type of CPU chip inserted in said first socket and for generating an identification signal in response to the identification;

a clock signal generator, disposed on the circuit board and coupled to said identifying circuit and to said first socket, responsive to said identification signal for generating clock signals compatible with the type of CPU chip in the first socket;

an enabling circuit, disposed on the circuit board and coupled to said identifying circuit and said first socket, responsive to said identification signal for (a) enabling signals on said first output pin to be transmitted when one of said first type of CPU chips is in said first socket and (b) enabling signals on said second output pin to be transmitted when one of said second type of CPU chips is in said first socket, thereby allowing said particular output signal to be transmitted regardless of which one of said first and second types of CPU chips are in said first socket; and

a second socket disposed on the circuit board for receiving a second CPU chip, said second socket coupled to said clock signal generator, said clock signal generator providing clock signals compatible with the type of CPU chip in the second socket.

3. The computer system of claim 2, further comprising means, coupled to said first socket and to said second socket, responsive to a signal from a CPU chip in said first socket for disabling a CPU chip in said second socket.

4. The computer system of claim 2, further comprising means, coupled to said clock signal generator and to said first and second sockets, responsive to a signal from a CPU chip in said first socket for disabling said clock signal to said second socket.

9. The computer system of any of claims 2 or 5 wherein the first socket is adapted to receive a CPU chip selected from the group consisting of 80486DX and 80487SX microprocessor chips and the second socket is adapted to receive an 80486SX CPU chip.

5. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising;

a first socket, disposed on the circuit board, for receiving different types of CPU chips, wherein at least first and second of said different types of CPU chips drive a particular output signal on different first and second respective output pins, depending on the type of CPU chip;

an identifying circuit, disposed on the circuit board and coupled to said first socket, for identifying the type of CPU chip inserted in said first socket and for generating an identification signal in response to the identification;

a clock source generating first and second clock signals compatible with said first and second types of CPU chips;

a data selector, having inputs coupled to receive said first and second clock signals, a data selection control input coupled to receive said identification signal, and an output coupled to said first socket, whereby (a) said first clock signal is communicated to said first socket when said identification signal indicates that a CPU chip of said first type is in said first socket, and (b) said second clock signal is communicated to said first socket when said identification signal indicates that a CPU chip of said second type is in said first socket;

selecting means, disposed on the circuit board and coupled to said first socket, for (a) enabling signals on said first output pin to be transmitted when one of said first type of CPU chips are in said first socket and (b) enabling signals on said second output pin to be transmitted when one of said second type of CPU chips are in said first socket, thereby allowing said particular output signal to be transmitted regardless of which one of said first and second types of CPU chips are in said first socket; and

a second socket, disposed on the circuit board, for receiving a second CPU chip.

6. The computer system of claim 5, further comprising means, coupled to said selecting means and to said second socket, responsive to said selecting means for disabling a CPU chip in said second socket.

7. The computer system of claim 5, wherein said clock source further provides a third clock signal compatible with a CPU chip in said second socket.

8. The computer system of claim 7, further comprising means, interposed between said clock source and said second socket and responsive to a signal from a CPU chip in said first socket, for disabling said third clock signal to said second socket.

10. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a bus disposed on the circuit board for communicating address, data, and control signals, said bus including a particular output bus line for a particular output signal;

a first socket, disposed on the circuit board and coupled to said bus, for receiving different types of CPU chips, wherein at least first and second of said different types of CPU chips drive said particular output signal on different first and second respective output pins, depending on the type of CPU chip;

an identifying circuit, disposed on the circuit board and coupled to said first socket, for identifying the type of CPU chip inserted in said first socket and for generating an identification signal in response to the identification;

a clock signal generator, disposed on the circuit board and coupled to said identifying circuit and to said first socket, responsive to said identification signal for generating clock signals compatible with the type of CPU chip in the first socket; and

an enabling circuit, disposed on the circuit board and coupled to said identifying circuit and to said bus, responsive to said identification signal for (a) enabling signals on said first output pin to be transmitted to said particular output bus line when one of said first type of CPU chips is in said first socket and (b) enabling signals on said second output pin to be transmitted to said particular output bus line when one of said second type of CPU chips is in said first socket, thereby allowing said particular output signal to be transmitted to said particular output bus line, regardless of which one of said first and second types of CPU chips is in said first socket;

wherein said first socket includes engagement portions for said first and second output pins and said enabling circuit comprises;

an inverter having an input and an output, said input coupled to said identifying circuit;

a first tri-state gate having an input and an output and an enabling terminal, said input coupled to said bus to receive signals from said engagement portions for said first output pin, said enabling terminal coupled to said identifying circuit, and said output coupled to said bus; and

a second tri-state gate having an input and an output and an enabling terminal, said input coupled to said bus to receive signals from said engagement portion for said second output pin, said enabling terminal coupled to said output of said inverter, and said output coupled to said bus.

11. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a bus disposed on the circuit board for communicating address, data, and control signals, said bus including a particular output bus line for a particular output signal;

a first socket, disposed on the circuit board and coupled to said bus, for receiving different types of CPU chips, wherein at least first and second of said different types of CPU chips drive said particular output signal on different first and second respective output pins, depending on the type of CPU chip;

an identifying circuit, disposed on the circuit board and coupled to said first socket, for identifying the type of CPU chip inserted in said first socket and for generating an identification signal in response to the identification;

a clock signal generator, disposed on the circuit board and coupled to said identifying circuit and to said first socket, responsive to said identification signal for generating clock signals compatible with the type of CPU chip in the first socket;

an enabling circuit, disposed on the circuit board and coupled to said identifying circuit and to said bus, responsive to said identification signal for (a) enabling signals on said first output pin to be transmitted to said particular output bus line when one of said first type of CPU chips is in said first socket and (b) enabling signals on said second output pin to be transmitted to said particular output bus line when one of said second type of CPU chips is in said first socket, thereby allowing said particular output signal to be transmitted to said particular output bus line, regardless of which one of said first and second types of CPU chips is in said first socket; and

a second socket for receiving a second CPU chip, said second socket coupled to said bus and to said clock signal generator.

12. The computer system of claim 11, further comprising means, coupled to said first socket and to said second socket, responsive to a signal from a CPU chip in said first socket for disabling a CPU chip in said second socket.

13. A computer system of claim 11, further comprising means, coupled to said clock signal generator and to said first and second sockets, responsive to a signal from a CPU chip in said first socket for disabling said clock signal to said second socket.

14. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a bus disposed on the circuit board for communicating address, data, and control signals, said bus including a particular output bus line for a particular output signal;

a first socket, disposed on the circuit board and coupled to said bus, for receiving different types of CPU chips, wherein at least first and second of said different types of CPU chips drive said particular output signal on different first and second respective output pins, depending on the type of CPU chip;

an identifying circuit, disposed on the circuit board and coupled to said first socket, for identifying the type of CPU chip inserted in said first socket and for generating an identification signal in response to the identification;

a clock signal generator, disposed on the circuit board and coupled to said identifying circuit and to said first socket, responsive to said identification signal for generating clock signals compatible with the type of CPU chip in the first socket; and

an enabling circuit, disposed on the circuit board and coupled to said identifying circuit and to said bus, responsive to said identification signal for (a) enabling signals on said first output pin to be transmitted to said particular output bus line when one of said first type of CPU chips is in said first socket and (b) enabling signals on said second output pin to be transmitted to said particular output bus line when one of said second type of CPU chips is in said first socket, thereby allowing said particular output signal to be transmitted to said particular output bus line, regardless of which one of said first and second types of CPU chips is in said first socket;

a stabilizing circuit, coupled to said first socket; and

a second socket, disposed on the circuit board and coupled to said bus, to said first socket, and to said stabilizing circuit, for receiving a different type of CPU chip, said different type of chip having different pin assignments from the chip in the first socket.

15. An upgradeable/downgradeable central processing unit chip (CPU) computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a bus for communicating address, data, and control signals, said bus including a particular output bus line for a particular output signal;

at least one socket means, disposed on the circuit board and coupled to said bus, for plugging in different types of CPU chips, wherein at least first and second of said different types of CPU chips drive said particular output signal on different first and second respective output pins, depending on the type of CPU chip;

said socket means having engagement portions for said first and second output pins;

a clock signal generator, disposed on the circuit board and coupled to said socket means, for generating a clock signal compatible with the type of CPU Chip inserted in said socket means;

a first signal path coupled to said engagement portion for said first output pin, and a second signal path coupled to said engagement portion for said second output pin;

an identifying circuit, disposed on the circuit board and coupled to said socket means, for identifying the type of CPU chip inserted in said socket means and for generating an identification signal in response to the identification;

a clock source generating first and second clock signals compatible with said first and second types of CPU chips and a third clock signal compatible with a CPU chip in said second socket;

a data selector, having inputs coupled to receive said first and second clock signals, a data selection control input coupled to receive said identification signal, and an output coupled to said socket means, whereby (a) said first clock signal is communicated to said socket means when said identification signal indicates that a CPU chip of said first type is in said socket means, and (b) said second clock signal is communicated to said socket means when said identification signal indicates that a CPU chip of said second type is in said socket means; and

selector means, disposed on the circuit board and coupled to said signal paths and to said output bus line, for selecting one of said first and second signal paths for providing said particular output signal, said selection being responsive to the type of CPU chip in said socket means, thereby allowing said particular output signal to be transmitted to said output bus line, regardless of which one of said first and second types of CPU chips is in said socket means;

wherein said particular output signal is a floating point error signal (FERR#).

16. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a first socket, disposed on the circuit board, for receiving different types of CPU chips, wherein at least first and second of said different types of CPU chips drive a particular output signal on different first and second respective output pins, depending on the type of CPU chip;

a second socket, disposed on the circuit board, for receiving a second CPU chip different from the type of CPU chip for which said first socket is adapted;

an identifying circuit, disposed on the circuit board and coupled to said first and second sockets, for identifying the types of CPU chips inserted in said first and second sockets and for generating identification signals in response to the identifications;

a clock signal generator, disposed on the circuit board and coupled to said identifying circuit and to said first and second sockets, responsive to said identification signals for generating clock signals compatible either with the type of CPU chip in said first socket or, when a CPU chip has been inserted in said second socket, with the type of chip in said second socket; and

an enabling circuit, disposed on the circuit board and coupled to said identifying circuit and said first socket, responsive to said identification signal for (a) enabling signals on said first output pin to be transmitted when a CPU chip of said first type is in said first socket and (b) enabling signals on said second output pin to be transmitted when a CPU chip of said second type is in said first socket, thereby allowing said particular output signal to be transmitted regardless of which one of said first and second types of CPU chips is in said first socket.

17. The computer system of claim 16 further comprising means, coupled to said clock signal generator and to said first and second sockets, responsive to a signal from a CPU chip in said first socket for disabling said clock signal to said second socket.

18. The computer system of claim 16 wherein the first socket is adapted to receive a CPU chip selected from the group consisting of 80486DX and 80487SX microprocessor chips and the second socket is adapted to receive an 80486SX CPU chip.

19. The computer system of claim 16, further comprising means, coupled to said first socket and to said second socket, responsive to a signal from a CPU chip in said first socket for disabling a CPU chip in said second socket.

20. An upgradeable/downgradeable central processing unit (CPU) chip computer system for driving by more than one type of CPU chip, said computer system including a circuit board, the circuit board comprising:

a first socket, disposed on the circuit board, for receiving one of different types of CPU chips, wherein at least first and second of said different types of CPU chips drive a particular output signal on different first and second respective output pins, depending on the type of CPU chip;

an identifying circuit, disposed on the circuit board and coupled to said first socket, for identifying the type of CPU chip inserted in said first socket and for generating an identification signal in response to the identification;

a clock source generating first and second clock signals compatible with said first and second types of CPU chips;

a data selector, having inputs coupled to receive said first and second clock signals, a data selection control input coupled to receive said identification signal, and an output coupled to said first socket, whereby (a) said first clock signal is communicated to said first socket when said identification signal indicates that a CPU chip of said first type is in said first socket, and (b) said second clock signal is communicated to said first socket when said identification signal indicates that a CPU chip of said second type is in said first socket;

selecting means, disposed on the circuit board and coupled to said first socket, for (a) enabling signals on said first output pin to be transmitted when one of said first type of CPU chips are in said first socket and (b) enabling signals on said second output pin to be transmitted when one of said second type of CPU chips in said first socket, thereby allowing said particular output signal to be transmitted regardless of which one of said first and second types of CPU chips are in said first socket;

a second socket, disposed on the circuit board, for receiving a second type of CPU chip;

means, coupled to said selecting means and to said first socket, responsive to said selecting means for generating clock signals compatible with the type of CPU chip in the first socket;

means, coupled to said selecting means and to said second socket, responsive to said selecting means for disabling a CPU chip in said second socket; and

means, interposed between said clock source and said second socket and responsive to a signal from a CPU chip in said first socket, for disabling said third clock signal to said second socket.

21. The computer system of claim 20 wherein the first socket is adapted to receive a CPU chip selected from the group consisting of 80486DX and 80487SX microprocessor chips and the second socket is adapted to receive an 80486SX CPU chip.