Methods for producing integrated circuit devices

• US 5,547,906 A
• Filed: 07/13/1994
• Issued: 08/20/1996
• Est. Priority Date: 09/14/1992
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Pierre Badehi
• Inventors: Badehi, Pierre
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): BILODEAU, THOMA
• Application Number:
  US08/274,251
• Time in Patent Office: 769 Days
• Field of Search: 437/226, 437/227, 437/208, 437/915, 437/946
• US Class Current: 438/109
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method for producing integrated circuit devices including the steps of producing a plurality of integrated circuits on a wafer, each of the integrated circuits including a multiplicity of pads and thereafter slicing the wafer, thereby to define a plurality of integrated circuit elements, and wherein the step of slicing exposes sectional surfaces of the multiplicity of pads. Apparatus for carrying out the method and integrated circuit devices are also described and claimed.

Claims

1. A method of producing prepackaged integrated circuit devices comprising the steps of:

providing a wafer having a first surface and a second surface generally parallel to and oppositely directed with respect to said first surface;

producing a plurality of integrated circuit dies on said first surface of said wafer, each of the integrated circuit dies comprising a multiplicity of pads;

attaching a first electrically insulative plate to said plurality of integrated circuit dies on the first surface of said wafer;

separating the integrated circuit dies from each other so as to define edges thereof while the dies remain attached to the insulative plate;

generally surrounding said integrated circuits on said edges and said second surface with a protective sealant; and

thereafter slicing the wafer and protective sealant and the insulative plate attached thereto, thereby to define a plurality of prepackaged integrated circuit devices.

2. A method according to claim 1 and wherein the step of slicing exposes cross sectional surfaces of said multiplicity of pads.

3. A method according to claim 1 and also comprising the steps of providing a conductive layer over edges of the integrated circuits formed by the slicing step and electrically separating portions of the conductive layer electrically connected with separate ones of said multiplicity of pads.

4. A method according to claim 3 and wherein an electrical insulative layer is present along the sliced edges of said integrated circuits before the step of providing a conductive layer.

5. A method according to claim 3 and wherein said step of providing a conductive layer comprises forming a conductive coating also over non-edge portions of the integrated circuit.

6. A method according to claim 1 and wherein a plurality of wafers bearing integrated circuits are joined together in a stacked arrangement to provide multi-layer integrated circuit devices.

7. A method according to claim 1 and also comprising anti-corrosion treatment of electrical contacts of said integrated circuit devices including exposed pad edges.

8. A method of producing prepackaged integrated circuit devices comprising the steps of:

providing a wafer having a first surface and a second surface generally parallel to and oppositely directed with respect to said first surface;

producing a plurality of integrated circuit dies on said first surface of said wafer, each of the integrated circuit dies comprising a multiplicity of pads;

attaching a first electrically insulative plate to said plurality of integrated circuit dies on the first surface of said wafer;

separating the integrated circuit dies from each other so as to define edges thereof while the dies remain attached to the insulative plate;

generally surrounding said integrated circuit dies on said edges with a protective sealant;

attaching a second insulative plate to said plurality of integrated circuit dies on said second surface of said wafer; and

thereafter slicing the wafer and protective sealant and the insulative plates attached thereto, thereby to define a plurality of prepackaged integrated circuit devices.

10. A method according to claim 8 and wherein the step of slicing exposes sectional surfaces of said multiplicity of pads.

11. A method according to claim 8 and also comprising the steps of providing a conductive layer over sliced edges of the integrated circuits and electrically separating portions of the conductive layer communicating with separate ones of said multiplicity of pads.

12. A method according to claim 11 and wherein an electrical insulative layer is present along the sliced edges of said integrated circuits before the step of providing a conductive layer.

13. A method according to claim 11 and wherein said step of providing a conductive layer comprises forming a conductive coating also over non-edge portions of the integrated circuit.

14. A method according to claim 8 and wherein said slicing step is carried out at locations whereby the silicon substrate is not exposed at the sliced edges of the resulting integrated circuits.

15. A method according to claim 8 and wherein a plurality of wafers bearing integrated circuits are joined together in a stacked arrangement to provide multi-layer integrated circuit devices.

16. A method according to claim 8 and also comprising anti-corrosion treatment of electrical contacts of said integrated circuit devices including exposed pad edges.

9. A method of producing prepackaged integrated circuit devices comprising the steps of:

providing a wafer having an first surface and a second surface generally parallel to and oppositely directed with respect to said first surface;

producing a plurality of integrated circuit dies on said first surface of said wafer, each of the integrated circuit dies comprising a multiplicity of aluminum pads;

exposing the multiplicity of pads; and

applying anti-corrosion treatment to the multiplicity of pads, by employing a chromating solution.

17. A method according to claim 9 and also comprising the step of separating the integrated circuit dies from each other, thereby to define a plurality of integrated circuit devices.