Method and circuit for control of saturation current in voltage regulators

• US 5,548,205 A
• Filed: 06/07/1995
• Issued: 08/20/1996
• Est. Priority Date: 11/24/1993
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Monticelli, Dennis M.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): HAN, YOUNGHUIE JESSICA
• Application Number:
  US08/480,958
• Time in Patent Office: 440 Days
• Field of Search: 323/273, 323/274, 323/280, 323/281, 323/282, 323/284, 323/289, 323/351
• US Class Current: 323/274
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence

Abstract

A voltage regulator employs a PNP output transistor of vertical construction, which operates as a linear control element in a feedback controlled circuit which is formed in a substrate. A differential amplifier has one input coupled to a voltage reference and another input coupled via feedback from a resistive voltage divider connected between common and the output of the voltage regulator. A parasitic NPN transistor, which is merged physically and thermally with the structure of the PNP output transistor, senses the onset of output transistor saturation and re-routes the majority of the excess base current drive to a feedback control node. The feedback control node retards total excess drive via a reduction in drive amplifier gain and bandwidth thereby assuring good stability of feedback loop operation during all phases of saturation, without the need for additional frequency compensating elements.

Claims

1. A voltage regulator circuit comprising:

a vertical structure PNP transistor having an emitter, a base and a single collector, the emitter coupled to a voltage supply and the collector coupled to a load;

reference means for setting a desired potential provided by the single collector of the vertical structure PNP transistor to the load;

feedback means for sensing the potential across the load and generating a signal for controlling, through the base of the vertical structure PNP transistor, an amount of current flowing through the collector current of the vertical structure PNP transistor; and

saturation sensing means coupled to the vertical structure PNP transistor, operative to retard the signal generated by the feedback means when the vertical structure PNP transistor saturates.

2. The voltage regulator circuit of claim 1, wherein the reference means further comprises:

a fixed potential source.

3. The voltage regulator circuit of claim 1, wherein the feedback means comprises a differential amplifier.

4. The voltage regulator circuit of claim 1, wherein the saturation sensing means further comprises:

an NPN transistor formed within a substrate.

5. A voltage regulator circuit comprising:

a vertical structure PNP transistor formed within a substrate, having an emitter, a base and a single collector, the emitter coupled to a voltage supply and the collector coupled to a load;

reference means for setting a desired potential provided by the single collector of the vertical structure PNP transistor to the load;

feedback means for sensing the potential across the load and generating a signal for controlling, through the base of the vertical structure PNP transistor, an amount of current flowing through the collector of the vertical structure PNP transistor; and

saturation sensing means formed within the substrate, the saturation sensing means sharing at least one common region with the vertical structure PNP transistor, operative to retard the signal generated by the feedback means when the vertical structure PNP transistor saturates.

6. The voltage regulator circuit of claim 5, wherein the reference means further comprises:

a fixed potential source.

7. The voltage regulator circuit of claim 5, wherein the saturation sensing means further comprises:

an NPN transistor including a base-emitter region which also operates as a collector-base region of the vertical structure PNP transistor.

8. A voltage regulator circuit comprising:

a vertical structure transistor formed within a substrate, having its emitter coupled to a voltage supply and its collector coupled to a load;

reference means for setting a desired potential provided by the vertical structure transistor to the load;

feedback means for sensing the potential across the load and generating a signal for controlling through the base of the vertical structure transistor the collector of the vertical structure transistor, the feedback means comprising a driver transistor having its collector coupled to the base of the vertical structure transistor, operative to sense a drop in potential at the load and in response thereto to increase the current from the base of the vertical structure transistor; and

saturation sensing means formed within the substrate, the saturation sewing means sharing at least one common region with the vertical structure transistor, operative to retard the signal generated by the feedback means when the vertical structure transistor saturates.

9. A voltage regulator circuit comprising:

a vertical structure output transistor formed within a substrate, having an emitter, a base and a single collector, the emitter coupled to a voltage supply and the single collector coupled to a load;

reference means for setting a desired potential provided by the single collector of the vertical structure output transistor to the load;

feedback means for sensing the potential across the load and generating a signal for controlling, through the base of the vertical structure output transistor, an amount of current flowing through the collector of the vertical structure output transistor; and

a saturation sensing transistor formed within the substrate, an emitter of the saturation sensing transistor operative as the base of the output transistor, the saturation sensing transistor operative to retard the signal generated by the feedback means when the vertical structure output transistor saturates.

10. The voltage regulator circuit of claim 9, wherein the reference means further comprises:

a fixed potential source.

11. The voltage regulator circuit of claim 9, wherein the feedback means comprises:

a differential amplifier having a first input coupled to the reference means and a second input coupled to the single collector of the vertical structure output transistor.

12. The voltage regulator circuit of claim 9, wherein the vertical structure output transistor comprises:

a PNP transistor.

13. A method of regulating the potential provided to a load comprising the steps of:

coupling a voltage supply to a load through a vertical structure PNP transistor formed within a substrate, the vertical structure PNP transistor having an emitter, a base and a single collector, the emitter coupled to a voltage supply and single collector coupled to a load;

setting a desired potential to be provided by the single collector of the vertical structure PNP transistor to the load;

sensing the potential across load and generating a signal for controlling, through the base of the vertical structure PNP transistor, an amount of current flowing through the collector of the vertical structure PNP transistor; and

sensing saturation within the vertical structure PNP transistor, and in response thereto retarding the signal for controlling the amount of current flowing through the collector of the vertical structure PNP transistor.

14. The method of claim 13, wherein generating a signal for controlling further comprises the steps of:

dividing the potential across the load; and

comparing the divided potential to a reference potential.

15. The method of claim 13, wherein sensing saturation within the vertical structure PNP transistor further comprises the step of:

thermally sensing the vertical structure PNP transistor and in response thereto adjusting the level of the signal for controlling the amount of current flowing through the collector of the vertical structure PNP transistor.

16. The method of claim 15, wherein thermally sensing further comprises the step of:

thermally sensing the collector-base region of the vertical structure PNP transistor.

17. A method of regulating the magnitude of current drawn by a voltage regulator from a voltage supply comprising the steps of:

coupling a voltage supply to a load through a vertical structure transistor formed within a substrate, the vertical structure transistor having an emitter, a base and a single collector, the emitter coupled to the voltage supply and the collector coupled to the load;

sensing a potential across the load, comparing the sensed potential to a reference potential, the reference potential representative of a desired potential, and generating a control signal for controlling, through the base of the vertical structure transistor, an amount of current flowing through the collector of the vertical structure transistor;

sensing saturation within the vertical structure transistor with a thermally coupled parasitic transistor, an emitter of the thermally coupled parasitic transistor also operating as the base of the vertical structure transistor, and in response to sensed saturation, rerouting at least a portion of the control signal; and

decreasing the total magnitude of the control signal in response to the rerouting of the signal.

18. A method of regulating the magnitude of current drawn by a voltage regulator from a voltage supply comprising the steps of:

coupling a voltage supply to a load through a vertical structure transistor formed within a substrate, the vertical structure transistor having an emitter, a base and a single collector, the emitter coupled to the voltage supply and the collector coupled to the load;

sensing a potential across the load, comparing the sensed potential to a reference potential, the reference potential representative of a desired potential, and generating a control signal from a control amplifier for controlling, through the base of the vertical structure transistor, an amount of current flowing through the collector of the vertical structure transistor;

sensing saturation within the vertical structure transistor with a thermally coupled parasitic transistor, an emitter of the thermally coupled parasitic transistor also operating as the base of the vertical structure transistor, and in response to sensed saturation, rerouting at least a portion of the control signal; and

decreasing the total magnitude of the control signal in response to the rerouting of the signal by decreasing operating currents within the control amplifier.

19. A method of regulating the magnitude of current drawn by a voltage regulator from a voltage supply comprising the steps of:

coupling a voltage supply to a load through a vertical structure transistor formed within a substrate, the vertical structure transistor having an emitter, a base and a single collector, the emitter coupled to the voltage supply and the collector coupled to the load;

sensing a potential across the load, comparing the sensed potential to a reference potential, the reference potential representative of a desired potential, and generating a control signal from a control amplifier for controlling through the base of the vertical structure transistor, an amount of current flowing through the collector of the vertical structure transistor;

sensing saturation within the vertical structure transistor with a thermally coupled parasitic transistor, an emitter of the thermally coupled parasitic transistor also operating as the base of the vertical structure transistor, and in response to sensed saturation, rerouting at least a portion of the control signal; and

decreasing the total magnitude of the control signal in response to the rerouting of the signal by reducing a tail current fed to the control amplifier.

20. A method of regulating the magnitude of current drawn by a voltage regulator from a voltage supply comprising the steps of:

coupling a voltage supply to a load through a vertical structure transistor formed within a substrate, the vertical structure transistor having an emitter, a base and a single collector, the emitter coupled to the voltage supply and the collector coupled to the load;

sensing a potential across the load, comparing the sensed potential to a reference potential, the reference potential representative of a desired potential, and generating a control signal from a control amplifier for controlling through the base of the vertical structure transistor, an amount of current flowing through the collector of the vertical structure transistor;

sensing saturation within the vertical structure transistor with a thermally coupled parasitic transistor, an emitter of the thermally coupled parasitic transistor also operating as the base of the vertical structure transistor, and in response to sensed saturation, rerouting at least a portion of the control signal; and

decreasing the total magnitude of the control signal in response to the rerouting of the signal by sensing the level of current flowing through a collector of the thermally coupled parasitic transistor, and in response to an increase in such level, decreasing a tail current fed to the control amplifier.