Serial differential pass gate logic design

• US 5,548,231 A
• Filed: 06/02/1995
• Issued: 08/20/1996
• Est. Priority Date: 06/02/1995
• Status: Expired due to Term

• Current Assignee: AVM Technologies LLC
• Original Assignee: Translogic Technology Incorporated
• Inventors: Tran, Joseph
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/458,963
• Time in Patent Office: 445 Days
• Field of Search: 327/51, 327/52, 327/55, 327/57, 327/210, 327/213, 327/214, 327/219, 327/291, 327/379, 327/391, 326/21, 326/24, 326/113, 326/23, 365/196, 365/198, 365/207
• US Class Current: 327/52
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/1738 using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Abstract

A serial differential cell includes complementary positive and negative pass gate networks coupled to a differential amplifier, which produces a valid logic output. The complementary pass gate networks can include one or more pass gate stages coupled in series. In a serial differential multiplexer, a stage includes first and second inputs, and a select input for controlling which input is passed to an output of the stage. For multiple stages, the output of a first stage is coupled to one of the inputs of a next stage. A number of stages can be coupled together in series to form networks, with a differential amplifier coupled between positive and negative networks where necessary to provide a valid logic output.

Claims

1. A serial differential multiplexer cell comprising:

a pass gate network including a positive network and a negative network, the positive network having two or more inputs complementary to the negative network, the positive network having an output, and the negative network having an output complementary to the output of the positive network, the positive and negative networks having select nodes for selecting an input in the positive network and the complement of the input in the negative network to pass through to the outputs of the positive and negative networks; and

a differential amplifier for receiving the outputs from the positive and negative network and producing a valid logic output at an output node of the differential amplifier;

wherein the positive and negative networks each comprise at least one pass gate stage including two pass gates.

2. The serial differential cell according to claim 1 wherein the at least one pass gate stage comprises a first and second pass gate, the first and second pass gates each having an input and an output, the outputs of the first and second pass gates coupled together.

3. The serial differential cell according to claim 2 wherein the first and second pass gates each include an N-channel transistor.

4. The serial differential cell according to claim 1 wherein the differential amplifier has a complementary output node, and the serial differential cell further including additional positive and negative networks, the additional positive and negative networks having associated differential amplifiers with complementary output nodes coupled to corresponding outputs of the additional positive and negative networks, a first additional positive and negative network coupled to the output and the complementary output of the differential amplifier, respectively;

wherein the additional positive and negative networks each comprise at least one pass gate stage including two pass gates.

5. The serial differential cell according to claim 1 wherein the differential amplifier includes first and second transistors having gate nodes for receiving the outputs of the positive and negative networks, and further includes first and second pull-up transistors coupled in series with the first and second transistors, the first and second pull-up transistors having corresponding first and second gate nodes coupled to the output node and a complementary output node of the differential amplifier.

6. The serial differential cell according to claim 1 wherein the differential amplifier is coupled between a supply voltage node and a ground node, and a single transistor is positioned between the output of the differential amplifier and the ground node.

7. A serial differential multiplexer circuit comprising:

a positive pass gate network including a pass gate stage, and a negative pass gate network including a complementary pass gate stage, the complementary pass gate stages each including first and second input nodes, an output node, and a select node for selecting an input signal at the first or second input nodes to pass to the output node; and

a differential amplifier coupled between the output nodes of the positive and negative pass gate networks for receiving the input signals passed to the output nodes and producing a valid logic signal at a first output of the differential amplifier;

wherein the positive and negative networks each comprise at least one pass gate stage including two pass gates.

8. A method for selecting one of N input signals where N is greater than 1, in a multiplexer including complementary positive and negative pass gate networks, each network having N-1 pass gate stage or stages, and each of the complementary positive and negative pass gate networks including at least two pass gates, the method comprising:

in a final pass gate stage in the positive and negative networks, selecting one of two inputs, and a complement of the one of two inputs, to pass as an output signal and a complementary output signal of the positive and negative networks;

receiving the output signal and the complementary output signals at inputs of a differential amplifier coupled between a supply voltage and ground; and

producing a valid logic signal and a complement valid logic signal at complementary outputs of the differential amplifier.

9. A serial differential cell comprising:

a pass gate network including a positive network and a negative network, the positive network having two or more inputs complementary to the negative network, the positive network having an output, and the negative network having an output complementary to the output of the positive network, the positive and negative networks having select nodes for selecting an input in the positive network and the complement of the input in the negative network to pass through to the outputs of the positive and negative networks; and

a differential amplifier for receiving the outputs from the positive and negative network and producing a valid logic output at an output node of the differential amplifier;

wherein each of the positive and negative networks comprise more than one pass gate stage coupled in series.

10. The serial differential cell of claim 9 wherein the serial differential cell is a multiplexer for selecting N inputs, and each of the positive and negative networks comprise N-1 pass gate stages coupled in series, the N-1 stages having first and second input nodes, an output node, and a select node for selecting an input signal at the first or second input nodes to pass to the output node.

11. A serial differential cell comprising:

a pass gate network including a positive network and a negative network, the positive network having inputs complementary to the negative network, the positive network having an output, and the negative network having an output complementary to the output of the positive network, the positive and negative networks having select nodes for selecting an input in the positive network and the complement of the input in the negative network to pass through to the outputs of the positive and negative networks; and

a differential amplifier for receiving the outputs from the positive and negative network and producing a valid logic output at an output node of the differential amplifier; and

wherein the differential amplifier has the output node and a complementary output node, and the output node and the complementary output node are coupled to an input node and a complementary input node of a second positive and negative pass gate networks, respectively.

12. A serial differential multiplexer circuit comprising:

a positive pass gate network including a pass gate stage, and a negative pass gate network including a complementary pass gate stage, the stages including first and second input nodes, an output node, and a select node for selecting an input signal at the first or second input nodes to pass to the output node; and

a differential amplifier coupled between the output nodes of the positive and negative pass gate networks for receiving the input signals passed to the output nodes and producing a valid logic signal at a first output of the differential amplifier; and

wherein each of the positive and negative networks have more than one stage.

13. The serial differential multiplexer circuit of claim 12 wherein each of the positive and negative networks have two stages.

14. The serial differential multiplexer circuit of claim 12 wherein each of the positive and negative networks have three stages.

15. The serial differential multiplexer circuit of claim 12 wherein each of the positive and negative networks have four stages.

16. The serial differential multiplexer circuit of claim 12 wherein each of the positive and negative networks have five stages.

17. A method for selecting one of N input signals where N is greater than 1, in a multiplexer including complementary positive and negative pass gate networks, each network having N-1 pass gate stage or stages, the method comprising:

in complementary first pass gate stages, selecting one of two inputs, and a complement of the one of two inputs, to pass as an output signal and a complementary output signal of the complementary first pass gates;

in next complementary pass gate stages, receiving the output signal and the complementary output signal of the first complementary pass gate stages as a first input, and receiving another input signal and a complement of the another input signal as a second input;

selecting one of the first input and the complement to pass as an output signal of the next complementary pass gate stages;

in a final pass gate stage in the positive and negative networks, selecting one of two inputs, and a complement of the one of two inputs, to pass as an output signal and a complementary output signal of the positive and negative networks;

receiving the output signal and the complementary output signals at inputs of a differential amplifier coupled between a supply voltage and ground; and

producing a valid logic signal and a complement valid logic signal at complementary outputs of the differential amplifier.

18. The method of claim 17 including the steps of:

applying select signals, or complement select signals, to the N-1 stages in the positive and negative networks to select one of the N inputs to pass as an output signal.

19. The method of claim 17 including the steps of:

applying select signals, or complement select signals, to the N-1 stages coupled in series, each stage comprising a 2;

1 multiplexer; and

passing selected inputs to inputs of successive stages.