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Low power high speed CMOS current switching circuit

  • US 5,548,238 A
  • Filed: 01/05/1995
  • Issued: 08/20/1996
  • Est. Priority Date: 10/01/1993
  • Status: Expired due to Term
First Claim
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1. A high speed current switching circuit coupled and responsive to a digital signal having first and second signal levels, comprising:

  • first, second, third and fourth p-channel transistors, each having a source, a gate and a drain;

    the source of the first transistor being coupled to a first voltage, the drain of the first transistor being coupled to the source of the second transistor;

    the drain of the second transistor, the sources of the third and fourth transistors being coupled together;

    the drain of the third transistor being coupled to a second voltage which is a lower voltage than the first voltage;

    the drain of the fourth transistor being coupled to a current output for the current switching circuit;

    the gate of the first transistor being coupled to a first bias voltage so that the gate to source voltage of the first transistor establishes a predetermined current through the first transistor when the second transistor is switched on;

    the gate of the fourth transistor being coupled to a third voltage intermediate the first digital signal level and the second digital signal level of the digital signal; and

    means responsive to the digital signal changing from said first digital signal level to said second digital signal level, for switching on the second transistor to direct the predetermined current through the third transistor, and then switching off the third transistor to steer the predetermined current from the third transistor to the fourth transistor;

    said means also for switching the fourth transistor on to provide the predetermined current through the fourth transistor.

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