Radio receiver-transmitter apparatus and signal changeover switch

• US 5,548,239 A
• Filed: 05/10/1994
• Issued: 08/20/1996
• Est. Priority Date: 05/21/1993
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kohama, Kazumasa
• Primary Examiner(s): FAILE, ANDREW I
• Application Number:
  US08/245,441
• Time in Patent Office: 833 Days
• Field of Search: 455/78, 455/82, 455/83, 327/408, 327/416, 327/427, 327/436, 333/101, 333/103, 333/104, 333/262, 307/111, 307/112, 307/115
• US Class Current: 327/408
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A radio receiver-transmitter apparatus equipped with a signal changeover switch which is capable of properly dealing with a high-power radio frequency signal and ensuring a desired insertion loss and superior isolation characteristic. The switch has a signal input terminal, a signal output terminal and a signal input-output terminal, and comprises a 1st FET unit connected to the input terminal and the input-output terminal, a 2nd FET unit connected to the input terminal and the ground, a 3rd FET unit connected to the output terminal and the input-output terminal, and a 4th FET unit connected to the output terminal and the ground. The gate width of each transistor in the 1st FET unit is so determined as to render the source-drain saturation current greater than the maximum current amplitude of the input signal fed from the input terminal, and each of the 2nd and 3rd FET units consists of one or more transistor stages equal in number to the result of rounding up the numerical value which is obtained by dividing the maximum voltage amplitude of the input signal fed from the signal input terminal, by the withstand voltage of the transistors in the 2nd and 3rd FET units.

Claims

1. A signal changeover switch having a signal input terminal, a signal output terminal and a signal input-output terminal, and comprising first, second, third and fourth units of field-effect transistors;

wherein one end of said first FET unit is connected to the signal input terminal while the other end thereof is connected to the signal input-output terminal;

one end of said second FET unit is connected to the signal input terminal while the other end thereof is grounded;

one end of said third FET unit is connected to the signal output terminal while the other end thereof is connected to the signal input-output terminal;

one end of said fourth FET unit is connected to the signal output terminal while the other end thereof is grounded;

each of the transistors constituting said first FET unit has a gate width so determined as to render the source-drain saturation current greater than the maximum current amplitude of the input signal fed from the signal input terminal;

said second FET unit consists of one or more transistor stages equal in number to the result of rounding up the numerical value which is obtained by dividing the maximum voltage amplitude of the input signal fed from the signal input terminal, by the withstand voltage of the transistors in said second FET unit; and

said third FET unit consists of one or more transistor stages equal in number to the result of rounding up the numerical value which is obtained by dividing the maximum voltage amplitude of the input signal fed from the signal input terminal, by the withstand voltage of the transistors in said third FET unit.

2. The switch according to claim 1, wherein the number of transistor stages in said first FET unit is so determined as to minimize the insertion loss and the isolation value in said first FET units;

and

the gate width of each of the transistors constituting said second and third FET units is so determined as to minimize the insertion loss and the isolation value in said second and third FET units.

3. The switch according to claim 2, wherein the number of transistor stages in said fourth FET unit is determined in dependence on the power of the received signal, and the gate width of each of the transistors constituting said fourth FET unit is so determined as to minimize the insertion loss and the isolation value in said fourth FET unit.