System for switching power and scrubbing power mixing devices for faults

• US 5,548,463 A
• Filed: 01/11/1996
• Issued: 08/20/1996
• Est. Priority Date: 06/30/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Kagy, Carl, Sonnier, David P., Brown, David, Bunton, William P., Bissell, Stephen R., Aldridge, David L., Gunn, Daniel D.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US08/578,883
• Time in Patent Office: 222 Days
• Field of Search: 323/269, 323/272, 307/43, 307/48, 361/18, 363/13-15, 363/34, 363/65, 363/89, 324/500, 324/522, 324/523, 324/537, 324/765, 324/767-769, 324/527
• US Class Current: 361/18
• CPC Class Codes: G01R 31/40 Testing power supplies testing photovoltaic devices H02S50/10
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: H02J 9/061 for DC powered loads

Abstract

A power switching circuit module includes two power rails coupling independent power supplies to the input of a DC controller and test circuits to detect latent faults in power mixing devices included in the circuit.

Claims

1. In a power circuit supplying power from multiple power supplies to device having a power input port, a system for detecting latent faults in power mixing devices comprising:

a first power rail coupling a first power source to the power input port, said first power rail including a first power pass transistor and a first isolation diode coupled in series, and having a first test node between said first power pass transistor and said first isolation diode, with said first isolation diode for coupling said first test node to the power input port of the device and for isolating the first test node from other power sources unless said first isolation diode has a short circuit fault;

a second power rail coupling a second power source to the power input port, said second power rail including a second power pass transistor and a second isolation diode coupled in series, and having a second test node between said second power pass transistor and said second isolation diode, with said second isolation diode for coupling said second test node to the power input port of the device and for isolating the second test node from other power sources unless said second isolation diode has a short circuit fault;

a first switching circuit, coupled to receive a first enable signal and coupled to said first power pass transistor, for turning on said first power pass transistor when said first enable signal is asserted to couple said first power source to said first test node to energize said first test node unless said first power pass transistor has an open circuit fault;

a second switching circuit, coupled to receive a second enable signal and coupled to said second power pass transistor, for turning on said second power pass transistor when said second enable signal is asserted to couple said second power source to said second test node to energize said second test node unless said second power pass transistor has an open circuit fault;

a first test circuit, coupled to said first test node, for asserting a first OK signal if said first test node is energized;

a second test circuit, coupled to said second test node, for asserting a second OK signal if said second test node is energized, where said first OK signal is negated in the case where said first enable signal is asserted and said power pass transistor has an open circuit fault so that a latent open circuit in the first power pass transistor can be detected, and where said first OK signal is asserted in the case where said first enable signal is negated, said second enable signal is asserted and said first isolation diode has a short circuit fault so that said first isolation diode can be scrubbed for faults.

2. The system of claim 1 wherein:

said first test circuit includes an opto-isolator, having a diode control input coupled to said first test node, for asserting said first OK signal when said first test node is energized.

3. The system of claim 1 wherein:

said first power rail further comprises an energy-limiting fuse connected in series between the first power source and said first test node where said first OK signal is negated if said first enable signal is asserted and said fuse has an open circuit fault.

4. The system of claim 1 further comprising:

a control unit, coupled to said first and second switching circuits and said first and second test circuits, for monitoring said OK signals when said enable signals are asserted and negated to scrub said diodes for faults.