LAN interface with simplified overcurrent protection

• US 5,548,467 A
• Filed: 02/14/1994
• Issued: 08/20/1996
• Est. Priority Date: 02/14/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rasmus, Todd M., Heaney, James A.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): JACKSON, STEPHEN W
• Application Number:
  US08/195,246
• Time in Patent Office: 918 Days
• Field of Search: 361/93, 361/62, 361/64, 361/66, 361/71, 361/88, 361/18, 361/31, 323/277, 323/275
• US Class Current: 361/93.7
• CPC Class Codes: H02H 3/087 for dc applications
• CPC Class Codes: H04L 12/40045 Details regarding the feeding of energy to the node from the bus

Abstract

A local area network (LAN) interface port with a simple overcurrent protection circuit which isolates the power supply connection for the port from fault conditions on the LAN. The circuit has a normally-on field effect pass transistor in line with the load terminal. The pass transistor shuts off when a fault condition is detected. Such a condition is detected when the voltage across a sense resistor becomes greater than the voltage across a reference resistor. A current mirror is made up of a transistor array and the sense and reference resistors. The current mirror compares the two voltages, and a bipolar transistor switches the gate voltage of the pass transistor on when the fault condition is detected. The design is particularly useful with the LAN system specified in ANSI/IEEE Standard 802.3, commonly known as Ethernet.

Claims

1. An overcurrent protection circuit comprising:

one input voltage terminal;

a load terminal;

a normally-on field-effect pass transistor and a sense resistor disposed in series between the input voltage terminal and the load terminal, the pass transistor being turned off by a voltage at a gate terminal;

a transistor array having first, second, third and fourth terminals, and having the second terminal connected to the load terminal;

a reference resistor connected between the first terminal of the transistor array and a point between the pass transistor and the sense resistor;

means for providing a constant reference current through the reference resistor, the means disposed between the third terminal of the transistor array and ground;

a resistor disposed to receive current flowing from the fourth terminal of the transistor array to ground;

a resistor disposed between the input voltage terminal and the gate of the pass transistor; and

one NPN transistor disposed for current sensing having an emitter terminal connected to ground, a base terminal connected to the resistor receiving current from the fourth terminal of the transistor array, and a collector terminal connected to apply a voltage to the gate terminal of the pass transistor so that when the current flowing from the fourth terminal of the transistor array to ground is substantially less than the constant current, the pass transistor is shut off.

2. The overcurrent protection circuit of claim 1 wherein the transistor array comprises:

first and second PNP transistors, the first PNP transistor having an emitter terminal coterminous with the first terminal of the transistor array, and having base and collector terminals both coterminous with the third terminal of the transistor array, the second PNP transistor disposed between the second and fourth terminals of the transistor array and having a base terminal connected to the base terminal of the first PNP transistor.

3. The overcurrent protection circuit of claim 1 further comprising:

a resistor disposed between the fourth terminal of the transistor array and the base terminal of the NPN transistor;

a pair of resistors disposed in series between the collector terminal of the NPN transistor and the input voltage terminal; and

a resistor and a capacitor disposed in series between the gate terminal of the pass transistor and ground, and having a point in between the resistor and the capacitor connected to a point in between the two resistors of the pair of resistors.

4. The overcurrent protection circuit of claim 3 wherein the transistor array comprises:

first and second PNP transistors, the first PNP transistor having an emitter terminal coterminous with the first terminal of the transistor array, and having base and collector terminals both coterminous with the third terminal of the transistor array, the second PNP transistor disposed between the second and fourth terminals of the transistor array and having a base terminal connected to the base terminal of the first PNP transistor.

5. An overcurrent protection circuit according to any of claims 1, 3, 2, or 4 wherein the means for providing a constant reference current comprises a single fixed resistor.

6. A circuit card having one or more local area network (LAN) interface subsystems, each subsystem comprising:

one power supply terminal;

a LAN connector;

circuitry for LAN signaling and control;

one or more coupling transformers disposed between the circuitry for LAN signaling and control and the LAN connector; and

an overcurrent protection circuit disposed between the power supply terminal and the LAN connector, the overcurrent protection circuit comprising;

an input terminal connected to the power supply terminal;

a load terminal connected to a terminal in the LAN connector;

a normally-on field-effect pass transistor and a sense resistor disposed in series between the input terminal and the load terminal, the pass transistor being turned off by a voltage at a gate terminal;

a transistor array having first, second, third and fourth terminals, and having the second terminal connected to the load terminal;

a reference resistor connected between the first terminal of the transistor array and a point between the pass transistor and the sense resistor;

means for providing a constant reference current through the reference resistor, the means disposed between the third terminal of the transistor array and ground;

a resistor disposed to receive current flowing from the fourth terminal of the transistor array to ground;

a resistor disposed between the input voltage terminal and the gate of the pass transistor; and

one NPN transistor disposed for current sensing having an emitter terminal connected to ground, a base terminal connected to the resistor receiving current from the fourth terminal of the transistor array, and a collector terminal connected to apply voltage to the gate terminal of the pass transistor so that when the current flowing from the fourth terminal of the transistor array to ground is substantially less than the constant current, the pass transistor is shut off.

7. The circuit card of claim 6 wherein each overcurrent protection circuit further comprises:

a resistor disposed between the fourth terminal of the transistor array and the base terminal of the NPN transistor;

a pair of resistors disposed in series between the collector terminal of the NPN transistor and the input terminal; and

a resistor and a capacitor disposed in series between the gate terminal of the pass transistor and ground, and having a point in between the resistor and the capacitor connected to a point in between the two resistors of the pair of resistors.

8. The circuit card of claim 7 wherein each transistor array comprises:

first and second PNP transistors, the first PNP transistor having an emitter terminal coterminous with the first terminal of the transistor array, and having base and collector terminals both coterminous with the third terminal of the transistor array, the second PNP transistor disposed between the second and fourth terminals of the transistor array and having a base terminal connected to the base terminal of the first PNP transistor.

9. The circuit card of claim 6 wherein each transistor array comprises:

first and second PNP transistors, the first PNP transistor having an emitter terminal coterminous with the first terminal of the transistor array, and having base and collector terminals both coterminous with the third terminal of the transistor array, the second PNP transistor disposed between the second and fourth terminals of the transistor array and having a base terminal connected to the base terminal of the first PNP transistor.

10. A circuit card according to any of claims 6, 7, 9, or 8 wherein each means for providing a constant reference current comprises a single fixed resistor.