Finite impulse response filter for modulator in digital data transmission system
First Claim
1. A finite impulse response filter for shaping a complex signal, in the form of s digital data pulse train having an in-phase channel and a quadrature channel, in a digital data transmission system, comprising:
- a delay element for sequentially receiving in-phase and quadrature binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits for each of the in-phase and quadrature channels representing a most recent history of the past n data bits received by said delay element during the past n data cycle intervals;
an element for outputting m sampling bits per each data bit, said sampling bits corresponding to particular sampling points for said n data bits, anda memory device having at least (n+m) address lines for providing at least 2.sup.(n+m) address locations, said n data bits and m sampling bits providing an input to said address lines, said memory device providing a specific output value for each possible combination of address line inputs.
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Abstract
A finite impulse response (FIR) filter is provided for shaping a one bit serial digital data pulse train in a digital data transmission system. The filter comprises (i) a delay element for sequentially receiving binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits representing a most recent history of the past n data bits received by the delay element during the past n data cycle intervals; (ii) a sampling element for sampling the data pulse train at a rate of m samples per bit, and (iii) a memory device having at least (n 30 m) address lines for providing at least 2.sup.(n+m) address locations. The n data bits and m samples provide an input to the address lines, the memory device in response providing a specific precomputed and stored output value for each possible combination of address line inputs. The delay element may be implemented as a shift register and the memory device may be implemented as at least one programmable read only memory (PROM) integrated circuit. A counter circuit determines the beginning of each fixed data cycle interval and the rate at which said fixed data cycles occur, which rate is between 500 kilobits (Kbs) and sixteen megabits per second (Mbs). The filter operates as a 319 tap FIR filter at a data input rate of 500 Kbs and as a 19 tap FIR filter at a data input rate of 16 Mbs.
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Citations
18 Claims
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1. A finite impulse response filter for shaping a complex signal, in the form of s digital data pulse train having an in-phase channel and a quadrature channel, in a digital data transmission system, comprising:
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a delay element for sequentially receiving in-phase and quadrature binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits for each of the in-phase and quadrature channels representing a most recent history of the past n data bits received by said delay element during the past n data cycle intervals; an element for outputting m sampling bits per each data bit, said sampling bits corresponding to particular sampling points for said n data bits, and a memory device having at least (n+m) address lines for providing at least 2.sup.(n+m) address locations, said n data bits and m sampling bits providing an input to said address lines, said memory device providing a specific output value for each possible combination of address line inputs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of shaping a complex signal, in the form of a serial digital data pulse train having an in-phase channel and a quadrature channel, in a digital data transmission system, comprising the steps of:
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sequentially receiving in-phase and quadrature binary data bits in the data pulse train at fixed data cycle intervals; outputting simultaneously in parallel a plurality n of data bits for each of the in-phase and quadrature channels representing a most recent history of the past n data bits received during the past n data cycle intervals; sampling said data bits at a rate of m sampling bits per each data bit, and inputting said n data bits and said m sampling bits into a memory device having at least (n+m) address lines for providing at least 2.sup.(n+m) address locations; and outputting a specific output value for each possible combination of address line inputs. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification