Half-band filter and method

• US 5,548,542 A
• Filed: 09/12/1994
• Issued: 08/20/1996
• Est. Priority Date: 08/14/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Damerow, David H., Rauth, Cindy C., Frogge, Perry W.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US08/304,433
• Time in Patent Office: 708 Days
• Field of Search: 364/724.16, 364/724.13, 364/724.1, 364/724.01
• US Class Current: 708/319
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 19/00 Networks using time-varying elements, e.g. N-path filters

Abstract

A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing saturation compensation together with accumulator overflow compensation by monitoring bits more significant than the output bits.

Claims

1. A digital filter comprising:

a first data stream input port for N-bit data samples;

first and second multipliers for downconverting said data samples;

adders for summing partial products of the downconverted data samples and filter coefficients, and with the K least significant bits of each partial product ignored for K a positive integer;

third and fourth multipliers for upconverting the summed partial products, said adders being connected between pairs of said multipliers; and

a local oscillator for providing sines and cosines to said multipliers for up and down conversion.

2. The filter of claim 1, wherein:

said multipliers and adders are partitioned into two separate series of said multipliers and adders to form an odd coefficient filter arm and an even coefficient filter arm; and

all but one of said filter coefficients in the partial products in said even coefficient arm are zero, whereby said filter forms a half-band filter.

3. The filter of claim 2, further comprising:

(a) a second data stream input port coupled to said even coeffeicient filter arm;

(b) with (i) said first multiplier having inputs coupled to said first data stream input port and said cosines of said local oscillator, and output coupled to said odd coefficient filter arm, (ii) said second multiplier having inputs coupled to said sines of said local oscillator and to a multiplex of said second data stream input port and said first data stream input port, and output coupled to said even coefficient filter arm, (iii) said third multiplier having inputs coupled to said odd coefficient arm and said cosines of said local oscillator, and output coupled to a first filtered data stream output port, and (iv) said fourth multiplier having inputs coupled to said even coefficient filter arm and said sines of said local oscillator, and output coupled to both said first filtered data stream output port and a second filtered data stream output port.

4. The filter of claim 3, wherein:

(a) said local oscillator outputs only sines and cosines of multiples of π

/2; and

(b) each of said first, second, and fourth multipliers is a true/complementer with saturation compensation and said third multiplier is a true/complementer with both saturation compensation and accumulator overflow compensation.

5. A digital filter comprising:

two ports for receiving streams of data bits;

an odd coefficient filter arm comprising a first of said input ports, a first downconversion multiplier, a first finite impulse response (FIR) filter, and a first upconversion multiplier all coupled in series;

an even coefficient filter arm comprising a second of said input ports, a second downconversion multiplier, a second FIR filter, and a second upconversion multiplier all coupled in series; and

an oscillator for providing sines and cosines, the sines being provided to said second downconversion multiplier and to said second upconversion multiplier, the cosines being provided to said first downconversion multiplier and to said first upconversion multiplier.

6. The digital filter of claim 5 wherein said second FIR filter includes coefficients, all but one of which are zero, whereby the digital filter is a half-band filter.

7. The digital filter of claim 5 wherein said first and second FIR filters sum partial products of (a) filter coefficients and (b) said streams of data bits, and the K least significant data bits of the partial products are ignored.

8. The digital filter of claim 5 further comprising a first output port for a stream of filtered data coupled to said first upconversion multiplier, and a second output port for a stream of filtered data coupled to said second upconversion multiplier and to said first output port.

9. The digital filter of claim 5 wherein said sines and cosines are multiples of π

/2.

10. The digital filter of claim 5 further comprising a multiplexer coupled in series between said second input port and said second downconversion multiplier, and coupled to said first input port.

11. The digital filter of claim 5 further comprising means coupled to the digital filter for selecting one of the following operating modes for the digital filter:

decimation by two filtering, and interpolation by two filtering.

12. The digital filter of claim 11 wherein said operating modes selectable by said means for selecting further comprise quadrature downconversion of I and Q channels with decimation by two filtering, and interpolation by two filtering of complex baseband signal and quadrature upconversion.