Method and device for improved programming threshold voltage distribution in electrically programmable read only memory array

• US 5,548,549 A
• Filed: 03/07/1995
• Issued: 08/20/1996
• Est. Priority Date: 09/30/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ong, Tong-Chern
• Primary Examiner(s): DINH, SON T
• Application Number:
  US08/399,777
• Time in Patent Office: 532 Days
• Field of Search: 365/185, 365/63, 365/100, 365/104, 365/71, 365/148, 365/159, 365/174, 365/185.05
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A method and device to compensate for the series resistance effect along, for example, the source region in an electrically programmable read only memory array is described. One or more resistors are provided between the ground contact and ground. When a cell is programmed, the source is coupled to ground through one or more of the resistors, such that the resistance between source and ground for all cells is approximately equal. Therefore, the potential of the source of each cell is approximately equal for all cells during programming. In this way, the potential difference between the control gate and source is approximately equal for every cell, thereby resulting in more uniform programming levels and therefore more uniform threshold voltages. The method and device of the present invention is particularly applicable to multi-level cells, which employ several different threshold voltages to represent several different logic states. In addition to providing for uniform threshold voltages, the resistors of the present invention can be used to provide for programming to different levels using a single programming voltage on the control gate. For each level, the source of a cell is coupled to ground through one or more resistors, such that the potential difference between the control gate and the source has the appropriate value for that level.

Claims

1. An array of MOS devices comprising:

a plurality of MOS devices, each of said MOS devices having a first region and a control gate, wherein said first regions of said plurality of MOS devices are coupled in series to a first node;

a plurality of first resistors coupled to said first node and a first potential; and

,

a plurality of first switches coupled to said first potential and said first node, and disposed between each of said plurality of said first resistors, such that said first node is switchably coupled to said first potential through one or more of said first resistors.

2. The array as described in claim 1 wherein said first potential is a ground potential.

3. The array as described in claim 1 wherein each of said MOS devices is an electrically programmable memory device further comprising a floating gate, and wherein said first region comprises a source region.

4. The array as described in claim 1 wherein all of said first resistors each have an approximately equal resistance value, and wherein said resistance value is approximately equal to an average resistance between said first regions of adjacent ones of said electrically programmable memory devices.

5. An array of MOS devices comprising:

a plurality of MOS devices, each of said MOS devices having a first region and a control gate, wherein said first regions of said plurality of MOS devices are coupled in series to a first node; and

,

means for selecting a resistance value between said first node and a first potential, wherein each said MOS devices is an electrically programmable memory device further comprising a floating gate, and wherein the resistance value comprises one of a plurality of discrete values.

6. The array as described in claim 5 wherein said first potential is a ground potential.

7. The array as described in claim 6 wherein said first region comprises a source region.

8. A method of programming an electrically programmable memory device, said memory device comprising a plurality of memory cells, each of said memory cells having a first region and a control gate, wherein said first regions of said plurality of memory cells are coupled in series to a first node, said method comprising the steps of:

applying a first potential to said control gate;

coupling said first node to a second potential through a first set of a plurality of first resistors for each of said plurality of cells having a first resistance between said first region and said first node, and coupling said first node to said second potential through a second set of the plurality of first resistors for each of said plurality of cells having a second resistance between said first region and said first node, wherein said first set of resistors and said second set of resistors are selected by enabling one or more of a plurality of first switches, wherein each of said first switches is coupled between the first node and the second potential, and is disposed between each of the plurality of first resistors.

9. The method as described in claim 8 wherein said second potential is a ground potential.

10. A method of programming an electrically programmable memory device, said memory device comprising a plurality of memory cells, each of said memory cells having a first region and a control gate, wherein said first regions of said plurality of memory cells are coupled in series to a first node, said method comprising the steps of:

applying a first potential to said control gate; and

,

providing a first resistance value between said first node and a second potential, wherein said first resistance value is one of a plurality of discrete values, and wherein said first resistance value depends upon a second resistance between said first region of said cell being programmed and said first node.

11. The method as described in claim 10 wherein said second potential is a ground potential.