Method and apparatus for providing high-speed column redundancy

• US 5,548,553 A
• Filed: 12/12/1994
• Issued: 08/20/1996
• Est. Priority Date: 12/12/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Leary, Michael, Cooper, Elizabeth M.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/353,603
• Time in Patent Office: 617 Days
• Field of Search: 365/96, 365/200, 365/201, 365/230.02, 365/51, 365/189.02, 365/189.05, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 29/80 with improved layout
• CPC Class Codes: G11C 29/802 by encoding redundancy signals
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.

Claims

1. A method for correcting at least one defect in a memory device comprising the steps of:

providing at least one redundant column in a memory array having a plurality of columns, said plurality of columns coupled to a bus having a corresponding plurality of bit locations, each of said columns having an input path and an output path, wherein said output path further comprises a plurality of 2-input multiplexers corresponding to said plurality of bit locations, said input and output paths coupled to said corresponding bit location of said bus; and

rearranging the correspondence between said bits on said bus and columns of memory in response to one of said plurality of columns being defective, such that the redundant column stores data for one of said columns of said plurality of columns and another of said columns of said plurality of columns stores data for said defective column, said step of rearranging comprising the step of coupling neighboring pairs of said columns to the inputs of said plurality of 2-input multiplexers, including coupling said redundant column to the input of one said plurality of 2-input multiplexers, and wherein the output of said multiplexer provides output from either one of said pair of columns to said bus.

2. A method for correcting at least one defect in a memory device comprising the steps of:

providing at least one redundant column in a memory array having a plurality of columns, said plurality of columns coupled to a bus having a corresponding plurality of bit locations, each of said columns having an input path and an output path, said input and output paths coupled to said corresponding bit location of said bus; and

bypassing one of said plurality of columns in the event that said one of said columns is defective, said step of bypassing said one of said columns comprising the step of coupling said bit locations of said bus corresponding to said columns between said defective column and said redundant column, including said bit location of said bus corresponding to said defective column, to said input and output path of said column adjacent to said corresponding column in the direction of the redundant column said step of bypassing further comprising the step of coupling neighboring pairs of said columns to the inputs of a plurality of 2-input multiplexers, including coupling said redundant column to the input of one said plurality of 2-input multiplexers, and wherein the output of said multiplexer provides output from either one of said pair of columns to said bus.

3. A memory device comprising:

a memory array comprising a plurality of columns of data each of said columns having an input and an output path, said input and output paths coupled to a bus, said bus comprising a plurality of locations corresponding to said plurality of columns;

at least one redundant column of data, said redundant column of data accessed substantially simultaneously with said memory array; and

means, responsive to one of said columns of said memory being defective, for rearranging the correspondence between said bits on said bus and columns of memory to allow the redundant column to store data for one of said columns of said plurality of columns and to allow another of said columns of said plurality of columns to store data for said defective column, said means for rearranging further comprising a plurality of 2-input multiplexers corresponding to a number of bits of said bus, each of said multiplexers coupling neighboring pairs of said columns to provide one output bit on said output bus.

4. The memory device of claim 3, wherein each of said plurality of columns further comprises:

input multiplexing means, coupled to receive input from said location on a bus corresponding to said respective column and from a location on said bus associated with a neighboring column.

5. The memory device of claim 4, wherein said input multiplexing means operates to receive data from said bus location associated with said neighboring column and said output multiplexing means operates to receive data from said neighboring column responsive to one of said plurality of columns being defective.

6. The memory device of claim 3, wherein said portion of said columns includes a set of columns located between said defective column and said redundant column.

7. The memory device of claim 6, further comprising means for storing a value indicating the number of columns in said portion of said columns.

8. The memory device of claim 6, further comprising means for storing a mask indicating which of said columns of said plurality of columns is included in said portion of said columns.

9. The memory device of claim 7 wherein said value is stored in a fuse.

10. The memory device of claim 7, wherein said value is stored in a register.